1. A semiconductor package, comprising:
an organic substrate;
a stiffness layer, formed on the organic substrate; and
a chip subassembly, disposed on the stiffness layer, the chip subassembly comprising at least a first chip, a second chip, and a third chip, the second chip being disposed between the first chip and the third chip in a stacked orientation, the second chip supporting proximity communication between the first chip and the third chip.
2. The semiconductor package according to claim 1, wherein:
the first, second and third chips respectively have first, second and third signal pads formed on a major surface thereof;
the second chip are arranged in face-to-face manner with the first chip and the third chip so that at least some of the second signal pads are capacitively) coupled to at least some of the first signal pads and at least some of the third signal pads;
the major surface of the second chip is spaced apart from the major surfaces of the first and third chips.
3. The semiconductor package according to claim 2, wherein the first and third chips are electrically connected to organic substrate by a plurality of bonding wires.
4. The semiconductor package according to claim 2, wherein each of the first chip and the third chip has a plurality of electric contacts, the stiffness layer has a plurality of vias, and the electric contacts of the first chip and the third chip are electrically connected to the organic substrate by the vias.
5. The semiconductor package according to claim 1, wherein each of the first chip and the third chip has a plurality of electric contacts, the stiffness layer has a plurality of vias, and the electric contacts of the first chip and the third chip are electrically connected to the organic substrate by the vias.
6. The semiconductor package according to claim 1, wherein the chip subassembly comprising a plurality of chips arranged in matrix.
7. A semiconductor package, comprising:
an organic substrate;
a chip subassembly, disposed on the organic substrate, the chip subassembly comprising at least a first chip, a second chip, and a third chip, the second chip being disposed between the first chip and the third chip in a stacked and flipped orientation, the second chip supporting proximity communication between the first chip and the third chip; and
a stiffness layer, disposed on the chip subassembly.
8. The semiconductor package according to claim 7, wherein each of the first chip and the third chip has a plurality of bumps with which the first chip and third chip are electrically connected to the organic substrate, the second chip has a plurality of bonding wires with which the second chip is electrically connected to the organic substrate, the stiffness layer has at least one opening whose position is corresponding to the position of the bonding wires.
9. The semiconductor package according to claim 7, wherein the organic substrate has a cavity for receiving the second chip.
10. The semiconductor package according to claim 7, wherein each of the first chip and the third chip has a plurality of metal pillars with which the first chip and the third chip are electrically connected to the organic substrate, the height of the metal pillars are substantially equal to the height of the second chip.
11. The semiconductor package according to claim 7, wherein:
the first, second and third chips respectively have first, second and third signal pads formed on a major surface thereof;
the second chip are arranged in face-to-face manner with the first chip and the third chip so that at least some of the second signal pads are capacitively coupled to at least some of the first signal pads and at least some of the third signal pads;
the major surface of the second chip is spaced apart from the major surfaces of the first and third chips.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bump fabrication process for forming a bump on a wafer having an active surface with a passivation layer and at least one bonding pad thereon such that the passivation layer exposes the bonding pad, the process comprising the steps of:
forming a patterned solder mask layer with a pattern over the active surface of the wafer, wherein the solder mask layer has at least one opening that exposes the bonding pad, and a cross-sectional area through a bottom-section of the opening is smaller than a cross-sectional area through a mid-section of the opening, while a cross-sectional area through a top-section of the opening is smaller than the cross-sectional area through the mid-section of the opening;
depositing a solder material into the opening;
conducting a reflow process so that the solder material inside the opening fuses together to form a bump; and
removing the solder mask layer.
2. The process of claim 1, wherein the bump is fabricated using leaded solder material or lead-free solder material.
3. The process of claim 1, wherein the step of forming the solder mask layer includes forming a first patterned photoresistant layer having at least one first opening therein such that the first opening exposes the bonding pad and that cross-sectional area through bottom-section of the first opening is smaller than cross-sectional area through a top-section of the first opening.
4. The process of claim 3, wherein the first patterned photoresistant layer is fabricated using liquid photoresist or dry film.
5. The process of claim 3, after the step of forming the first patterned photoresistant layer, further including forming a second patterned photoresistant layer over the first patterned photoresistant layer such that the second patterned photoresistant layer has at least a second opening that links up with the first opening and exposes the bonding pad and that cross-sectional area through bottom-section of the second opening is larger than cross-sectional area through top-section of the second opening.
6. The process of claim 5, wherein the second patterned photoresistant layer is fabricated using dry film.
7. The process of claim 1, wherein the solder material is in powder form or paste form.
8. The process of claim 1, wherein before the step of forming the solder mask layer, an under-ball-metallurgy layer is formed over the bonding pad so that the bump is disposed on the under-ball-metallurgy layer.
9. A bump fabrication process for forming a bump on a wafer having an active surface with a passivation layer and at least one bonding pad thereon such that the passivation layer exposes the bonding pad, the process comprising the steps of:
forming a pre-formed bump over the bonding pad of the wafer;
forming a patterned solder mask layer with a pattern over the active surface of the water, wherein the solder mask layer has at least one opening that exposes the pre-formed bump, and a cross-sectional area through a bottom-section of the opening is smaller than a cross-sectional area through a mid-section of the opening;
depositing a solder material into the opening;
conducting a reflow process so that the solder material inside the opening and the pre-formed bump fuse together to form a bump; and
removing the solder mask layer.
10. The process of claim 9, wherein a cross-sectional area through a top-section of the opening is smaller than the cross-sectional area through the mid-section of the opening.
11. The process of claim 9, wherein the solder material is fabricated using constituents that differ from the constituents inside the pre-formed bump.
12. The process of claim 9, wherein the bump is fabricated using leaded solder material or lead-free solder material.
13. The process of claim 9, wherein the step of forming the solder mask layer includes forming a first patterned photoresistant layer having at least one first opening therein such that the opening exposes the pre-formed bump and that cross-sectional area through bottom-section of the first opening is smaller than a cross-sectional area through a top-section of the first opening.
14. The process of claim 13, wherein the first patterned photoresistant layer is fabricated using liquid photoresist or dry film.
15. The process claim 13, after the step of forming the first patterned photoresistant layer, further including forming a second patterned photoresistant layer over the first patterned photoresistant layer such that the second patterned photoresistant layer has at least a second opening that links up with the first opening and exposes the pre-formed bump and that cross-sectional area through bottom-section of the second opening is larger than a cross-sectional area through top-section of the second opening.
16. The process of claim 15, wherein the second patterned photoresistant layer is fabricated using dry film.
17. The process of claim 9, wherein the solder material is in powder form or paste form.
18. The process of claim 9, before the step of forming the solder mask layer, further including forming an under-ball-metallurgy layer over the bonding pad so that the bump is disposed on the under-ball-metallurgy layer.
19. A bump fabrication process for forming at least a second bump on a wafer having an active surface with at least a first bump thereon, the process comprising the steps of:
forming a patterned solder mask layer with a pattern over the active surface of the wafer, wherein the solder mask layer has at least one opening that exposes the first bump, and a cross-sectional area through a bottom-section of the opening is smaller than a cross-sectional area through a mid-section of the opening;
depositing a solder material into the opening;
conducting a reflow process so that the solder material inside the opening and the first bump fuse together to form a second bump; and
removing the solder mask layer.
20. The process of claim 19, wherein a cross-sectional area through a top-section of the opening is smaller than the cross-sectional area through the mid-section of the opening.
21. The process of claim 19, wherein the solder material is fabricated using constituents that differ from the constituents inside the first bump.
22. The process of claim 19, wherein the first and second bumps are fabricated using leaded solder material or lead-free solder material.
23. The process of claim 19, wherein the step of forming the solder mask layer includes forming a first patterned photoresistant layer having at least one first opening therein such that the opening exposes the first bump and that cross-sectional area through a bottom-section of the first opening is smaller than a cross-sectional area through the top-section of the first opening.
24. The process of claim 23, wherein the first patterned photoresistant layer is fabricated using liquid photoresist or dry film.
25. The process of claim 23, after the step of forming the first photoresistant layer, further including forming a second patterned photoresistant layer over the first patterned photoresistant layer such that the second patterned photoresistant layer has at least a second opening that links up with the first opening and exposes the first bump and that cross-sectional area through bottom-section of the second opening is larger than cross-sectional area through ac top-section of the second opening.
26. The process of claim 25, wherein the second patterned photoresistant layer is fabricated using dry film.
27. The process of claim 19, wherein the solder material is in powder form or paste form.