1. Circuit comprising
signal input (11) for receiving an input signal (s(t)),
a digital output stage (15) being designed for operation at a supply voltage (VDD), the output stage (15) comprising
a series of two n-channel CMOS transistors (no1, no2; nsw1, nsw2) sensitive to voltages across transistor node pairs going beyond a voltage limit (Vmax),
a common node (17; SW1) between the two n-channel CMOS transistors (no1, no2; nsw1, nsw2),
an output port (16),
active voltage limiting means (14; INV3, pdio) being arranged between the signal input (11) and the common node (17; SW1) for limiting voltages (Vmax) at the common node (17; SW1) to the voltage limit (Vmax), the voltage limiting means (14; INV2, pdio) being controllable by the state of the input signal (s(t)) and comprising a plurality of transistors (pd, nd, pswn; INV3, pdio) for providing a limited and stable output voltage (VNM) at the common node (17; SW1), wherein one of the plurality of transistors is a p-channel CMOS transistor (pswn; pdio) serving as switch, the gate (18; 38) of the p-channel CMOS transistor (pswn; pdio) being controlled by the state of a signal derived from the input signal (s(t)).
2. The circuit of claim 1, wherein two of the plurality of transistors (pd, nd) are arranged as inverter for inverting the input signal (s(t)) in order to apply an inverted signal (svn(t)) to a gate (18; 38) of the p-channel CMOS transistor (pswn; pdio) that serves as switch.
3. The circuit of claim 2, comprising a pull-up resistor (Rp) being situated between the output port (16) and a node that is kept at a higher voltage (VDDH) that is greater than the supply voltage (VDD), the pull-up resistor (Rp) being provided to pull the drain (16) of one of the two n-channel CMOS transistors (no2) to the higher voltage (VDDH).
4. The circuit of claim 1 or 2, comprising a p-channel driver part with at least two p-channel CMOS transistors (po1, po2) arranged in series.
5. The circuit of claim 1 or 2, comprising a level shifter (22) providing for a voltage (VR) that is lower than the voltage limit (Vmax).
6. The circuit of claim 1 or 2, comprising speed boost means having at least one capacitive element (Cb) speeding up the turn-onturn-off behavior of one of the CMOS transistors (no1, no2; nsw1, nsw2; po1, po2).
7. The circuit of claim 6, wherein the charging of the capacitive element (Cb) depends on the state of a signal derived from the input signal (s(t)).
8. The circuit of claim 1 or 2 being made using a submicron fabrication process, preferably a deep submicron fabrication process.
9. Open-drain output stage comprising a circuit in accordance with one of the claims 1 or 2.
10. Push-pull-output stage comprising a circuit in accordance with one of the claims 1 or 2.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of removing an obstruction from a blood vessel, comprising the steps of:
providing an obstruction engaging element and a catheter having an interlocking structure attached thereto, the obstruction engaging element being movable from a position within a lumen of the catheter to a position outside the lumen of the catheter;
advancing the catheter into an obstruction;
withdrawing the catheter after the advancing step so that the interlocking structure remains within the obstruction, the interlocking structure being attached to the catheter and extending distally from the catheter; and
moving the element so that the element becomes entangled with the obstruction and the interlocking structure.
2. The method of claim 1, wherein:
the providing step is carried out with the interlocking structure being a loose, flexible structure;
the withdrawing step being carried out with the loose, flexible interlocking structure being held by the obstruction so that the loose, flexible structure remains within the obstruction.
3. The method of claim 2, wherein:
the advancing step is carried out with the interlocking structure being a loose, flexible structure which lies loosely against an outer wall of the catheter.
4. The method of claim 2, wherein:
the providing step is carried out with the flexible structure including at least one filament.
5. The method of claim 4, wherein:
the providing step is carried out with the filament having at least one radiopaque material attached thereto.
6. The method of claim 5, wherein:
the providing step is carried out with the radiopaque material being formed as discrete beads, tubes or coils on the filament.
7. The method of claim 2, wherein:
the providing step is carried out with the filament forming at least one closed loop.
8. The method of claim 7, wherein:
the providing step is carried out with the interlocking structure including at least four closed loops.
9. The method of claim 7, wherein:
the providing step is carried out with a plurality of closed loops having different sizes.
10. The method of claim 1, wherein:
the moving step is carried out by moving the element proximally into engagement with the obstruction after the withdrawing step.
11. The method of claim 1, wherein:
the providing step is carried out with the obstruction engaging element being naturally biased to an expanded position.
12. The method of claim 11, wherein:
the moving step is carried out by permitting the obstruction engaging element to expand.
13. The method of claim 11, wherein:
the moving step is carried out by rotating the obstruction engaging element so that the element becomes entangled with the interlocking structure.
14. The method of claim 1, further comprising the step of:
exposing part of the obstruction engaging element before completing the withdrawing step.
15. The method of claim 14, wherein:
the exposing step is carried out before beginning the withdrawing step.