1. An apparatus comprises:
a protection circuit to provide overvoltage protection and backflow current protection when used to charge a battery from an external power source, in which source voltage of the external power source exceeds nominal value of a rail voltage supplied by the battery, the protection circuit to accept the source voltage, but to ensure that node-to-node potential on circuit components do not exceed a specified value when the external power source is used to charge the battery and to prevent backflow current from the battery to the external power source when voltage of the external power source drops below voltage of the battery; and
a switching circuit to switch a mode of operation of the protection circuit between the overvoltage protection and the backflow current protection.
2. The apparatus of claim 1, wherein the switching circuit switches the mode of operation of the protection circuit by changing a bias applied to the protection circuit.
3. The apparatus of claim 2, wherein the protection circuit uses a floating well transistor, in which its gate is to be biased by the switching circuit when in the overvoltage protection mode of operation, to ensure that the node-to-node potential on the circuit components does not exceed the specified value.
4. The apparatus of claim 3, wherein the switching circuit receives input voltage from the external power source to be switched to establish the bias voltage to the floating well transistor during the overvoltage protection mode of operation.
5. An apparatus comprises:
a protection circuit to provide overvoltage protection and backflow current protection when an external voltage is received through a data transfer link and used to charge a battery, in which the external voltage exceeds nominal value of a rail voltage supplied by the battery, the protection circuit to accept the external voltage, but to ensure that node-to-node potential on circuit components do not exceed a specified value when the external voltage is used to charge the battery and to prevent backflow current from the battery to the data transfer link when the external voltage drops below battery voltage;
a biasing circuit to bias the protection circuit; and
a switching circuit to change the bias applied by the biasing circuit to selectively switch a mode of operation of the protection circuit between the overvoltage protection and the backflow current protection.
6. The apparatus of claim 5, wherein the protection circuit uses a floating well transistor, in which its gate is to be biased by the switching circuit when in the overvoltage protection mode of operation, to ensure that the node-to-node potential on the circuit components does not exceed the specified value.
7. A method of providing overvoltage protection and back flow current protection comprising:
linking an external voltage to charge a battery and to power circuitry of an integrated circuit powered by the battery;
providing a first biasing to a protection circuit to prevent excessive external voltage from being applied to the circuitry, when the external voltage is linked to the integrated circuit;
providing a second biasing to the protection circuit to prevent backflow current flow from the battery to external source of the external voltage, when the external voltage drops to a specified voltage below that of the battery; and
switching between overvoltage protection and backflow current protection modes of operation by switching in the first or second biasing based on a value of the external voltage.
8. The method of claim 7, wherein the linking links the external voltage as a component of a data transfer link.
9. The method of claim 7 wherein the linking links the external voltage as a component of a Universal Serial Bus.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A testing apparatus for testing a memory under test, comprising:
a pattern generator for generating an address signal and a data signal to be provided to the memory under test, and an expected value signal indicating an expected value that the memory under test outputs in a normal state, according to the address signal and the data signal;
a logic comparator for comparing an output signal outputted by the memory under test according to the address signal and the data signal with the expected value signal and outputting fail data when the output signal is not matched with the expected value signal, the fail data comprising a first fail data from a first test of the memory under test, a second fail data from a second test of the memory under test, and a third fail data from a third test of the memory under test;
a first fail buffer memory for storing the first fail data on an address indicated by the address signal;
a second fail buffer memory for accumulating the first fail data stored in the first fail buffer memory and the second fail data and storing the first and second fail data;
a fail data transmitting section for receiving the fail data from the logic comparator and one of the fail data stored in the first fail buffer memory and the fail data stored in the second fail buffer memory, performing an operation based on the received fail data, and providing a result of the operation to the first fail buffer memory or the second fail buffer memory; and
a first safe analysis section for performing a fail safe analysis on the memory under test with reference to the first fail data stored in the first fail buffer memory,
wherein
the first fail buffer memory accumulates the first and second fail data stored in the second fail buffer memory and the third fail data and stores the first second and third fail data, and
the first safe analysis section performs a fail safe analysis on the memory under test further with reference to the first and second fail data stored in the second fail buffer memory.
2. The testing apparatus according to claim 1 further comprising an OR circuit for performing an OR operation on the second fail data and the fail data stored in the first fail buffer memory and storing the result in the second fail buffer memory, and for performing an OR operation on the third fail data and the fail data stored in the second fail buffer memory and storing the result in the first fail buffer memory.
3. The testing apparatus according to claim 2 further comprising a first address fail memory for storing sequentialty the first fail data outputted by the logic comparator on the address indicated by the address signal, wherein
the first fail buffer memory accumulates and stores the fail data stored in the first address fail memory and the fail data stored in the second fail buffer memory, and
the second fail buffer memory accumulates and stores the fail data stored in the first address fail memory and the fail data stored in the first fail buffer memory.
4. The testing apparatus according to claim 3 further comprising a second address fail memory for storing sequentially the second fail data outputted by the logic comparator on the address indicated by the address signal, wherein
the second fail buffer memory accumulates and stores the fail data stored in the first fail buffer memory and the fail data stored in the second address fail memory in parallel with performing the third test of the memory under test.
5. The testing apparatus according to claim 4, wherein
the first address fail memory sequentially stores therein the third fail data outputted by the logic comparator on the address indicated by the address signal, and
the first fail buffer memory accumulates and stores the fail data stored in the second fail buffer memory and the fail data stored in the first address fail memory in parallel with performing a fourth test of the memory under test.
6. The testing apparatus according to claim 5 further comprising a delay circuit for delaying the fail data stored in the first address fail memory or the second address fail memory in order to match the timing at which the fail data stored in the first address fail memory or the second address fail memory is provided to the OR circuit with the timing at which the fail data stored in the first fail buffer memory or the second fail buffer memory is provided to the OR circuit and providing the delayed fail data to the OR circuit.
7. The testing apparatus according to claim 1 further comprising:
a third fail buffer memory for storing in parallel with the first fail buffer memory or the second fail buffer memory fail data that is the same as the fail data provided to the first fail buffer memory or the second fail buffer memory; and
a second safe analysis section for performing in parallel with the first safe analysis section a fail safe analysis on the memory under test with reference to the fail data stored in the third fail buffer memory.
8. The testing apparatus according to claim 1 further comprising a third safe analysis section for performing in parallel with the first safe analysis section a fail safe analysis of the memory under test with reference to the first fail data stored in the first fail buffer memory.
9. A testing method for testing a memory under test, comprising:
providing an address signal and a data signal to the memory under test;
comparing an output signal outputted by the memory under test according to the address signal and the data signal with an expected value signal indicating an expected value that the memory under test outputs in a normal state according to the address signal and the data signal, and generating fail data when the output signal in not matched with the expected value signal, the fail data comprising a first fail data from a first test of the memory under test, a second fail data from a second test of the memory under test, and a third fail data from a third test of the memory under test;
storing sequentially the first fail data on an address in a first address fail memory indicated by the address signal in parallel with performing a first test of the memory under test;
storing sequentially the second fail data on an address in a second address fail memory indicated by the address signal in parallel with performing a second test of the memory under test;
reading the fail data stored in the first address fail memory to a first fail buffer memory in parallel with performing the second test, and performing a fail safe analysis on the memory under test with reference to the fail data stored in the first fail buffer memory;
storing sequentially the third fail data on the address in the first address fail memory indicated by the address signal in parallel with performing a third test of the memory under test;
accumulating and storing in a second fail buffer memory the fail data stored in the first fail buffer memory and the fail data stored in the second address fail memory in parallel with performing the third test, and performing a fail safe analysis on the memory under test with reference to the first and second fail data stored in the second fail buffer memory; and
receiving the generated fail data and one of the fail data stored in the first fail buffer memory and the fail data stored in the second fail buffer memory, performing an operation based on the received data, and providing a result of the operation to the first fail buffer memory or the second fail buffer memory.