1. A method of operating a countertimer circuit, the method comprising:
determining a match condition by comparing a count value of the countertimer circuit with a value stored in a match register of the countertimer circuit; and
after the match condition is determined, delaying an assertion of the match condition based on a value programmed in a match companion register of the countertimer circuit that specifies a cycle number in which the match assertion will be delayed, wherein the match companion register is associated with the match register, wherein at least one of determining the match condition and delaying the assertion of the match condition is executed by a computing machine.
2. The method of claim 1, further comprising generating event signals within the countertimer circuit, wherein the delaying the assertion of the match condition comprises delaying the assertion of the match condition when at least one of the event signals satisfies a predefined condition.
3. The method of claim 2, wherein the delaying the assertion of the match condition comprises delaying the assertion of the match condition for one timer clock of the countertimer circuit after the match condition has occurred.
4. The method of claim 2, wherein the delaying the assertion of the match condition comprises allowing a dither cycle counter to advance to a next element in a dither pattern array when the at least one of the event signals satisfies the predefined condition.
5. The method of claim 2, wherein the generating the event signals comprises generating the event signals based on at least one of:
an input signal of the countertimer circuit,
an output signal of the countertimer circuit, and
a previous match condition of the countertimer circuit.
6. The method of claim 1 further comprising distributing timer cycles in which the assertion of the match condition will be delayed across all of the timer cycles of the countertimer circuit.
7. The method of claim 1, wherein the match condition is asserted by generating a timer match signal that is used to trigger an operation of application hardware.
8. The method of claim 1, wherein the delaying the assertion of the match condition comprising:
generating a timer match signal that is used to trigger an operation of application hardware;
delaying the timer match signal for one timer clock of the countertimer circuit; and
outputting the delayed timer match signal.
9. The method of claim 8, wherein the operation of the application hardware includes constructing a pulse-width modulated waveform.
10. The method of claim 1, wherein the determining the match condition comprises determining the match condition when the counter value is equal to the value stored in the match register.
11. A countertimer circuit comprising:
a counter;
a match module configured to determine a match condition by comparing a count value of the counter with a value stored in a match register of the countertimer circuit; and
a dither module configured to, after the match condition is determined, delay an assertion of the match condition based on a value programmed in a match companion register of the countertimer circuit that specifies a cycle number in which the match assertion will be delayed, wherein the match companion register is associated with the match register.
12. The countertimer circuit of claim 11 further comprising an event generation module configured to generate event signals, wherein the dither module is further configured to delay the assertion of the match condition when at least one of the event signals satisfies a predefined condition.
13. The countertimer circuit of claim 12, wherein the dither module is further configured to delay the assertion of the match condition for one timer clock of the counter after the match condition has occurred.
14. The countertimer circuit of claim 12, wherein the dither module comprises a dither cycle counter configured to advance to a next element in a dither pattern array when the at least one of the event signals satisfies the predefined condition.
15. The countertimer circuit of claim 12, wherein the event generation module is further configured to generate the event signals based on at least one of:
an input signal of the countertimer circuit,
an output signal of the countertimer circuit, and
a previous match condition of the countertimer circuit.
16. The countertimer circuit of claim 11, wherein the dither module is further configured to distribute timer cycles in which the assertion of the match condition will be delayed across all of the timer cycles of the counter.
17. The countertimer circuit of claim 11, wherein the dither module is further configured to generate a timer match signal that is used to trigger an operation of application hardware.
18. The countertimer circuit of claim 11, wherein the dither module is further configured to:
generate a timer match signal that is used to trigger an operation of application hardware;
delay the timer match signal for one timer clock of the counter; and
output the delayed timer match signal.
19. The countertimer circuit of claim 18, wherein the operation of the application hardware includes constructing a pulse-width modulated waveform.
20. The countertimer circuit of claim 11, wherein the dither module is further configured to determine the match condition when the counter value is equal to the value stored in the match register.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A light guide plate comprising:
a light incidence surface;
a light-emitting surface joining with the light incidence surface;
a diffraction grating having a plurality of slots formed on the light-emitting surface, wherein depths of the slots increase from a center of the diffraction grating to each of two opposite sides of the diffraction grating, and edges of the opposite sides are parallel to the slots; and
a bottom surface on an opposite side of the light guide plate to the light-emitting surface.
2. The light guide plate as claimed in claim 1, wherein a transverse width of each slot is in the range from 1 micron to 10 microns.
3. The light guide plate as claimed in claim 1, wherein a depth of each slot is in the range from 0.5 microns to 2 microns.
4. The light guide plate as claimed in claim 1, wherein the slots of the diffraction grating are parallel with the light incidence surface.
5. The light guide plate as claimed in claim 4, wherein a transverse width of each slot decreases along a direction away from the light incidence surface.
6. The light guide plate as claimed in claim 1, wherein the light guide plate is one of a flat sheet having uniform thickness and a wedge-shaped block.
7. A light guide plate comprising:
a light incidence surface;
a light-emitting surface joining with the light incidence surface;
a diffraction grating having a plurality of slots formed on the light-emitting surface, wherein a transverse width of each slot decreases along a direction away from the light incidence surface; and
a bottom surface on an opposite side of the light guide plate to the light-emitting surface.
8. The light guide plate as claimed in claim 7, wherein the transverse width of each slot is in the range from 1 micron to 10 microns.
9. The light guide plate as claimed in claim 7, wherein a depth of each slot is in the range from 0.5 microns to 2 microns.
10. The light guide plate as claimed in claim 7, wherein the slots of the diffraction grating are parallel with the light incidence surface.
11. The light guide plate as claimed in claim 7, wherein the light guide plate is one of a flat sheet having uniform thickness and a wedge-shaped block.