1. An apparatus, comprising:
an input control circuit configured to provide an input clock signal responsive to a data clock signal;
a delay circuit configured to delay the data clock signal corresponding to a propagation delay of a command signal;
an output control circuit configured to provide an output clock signal responsive to the delayed data clock signal; and
a buffer circuit configured to capture data responsive to the input clock signal, the buffer circuit further configured to provide the captured data responsive to the output clock signal.
2. The apparatus of claim 1, wherein the buffer circuit comprises:
an input circuit configured to latch the data responsive to the data clock signal;
a dual clocked storage element coupled to the input circuit and configured to latch the data responsive to the input clock signal; and
an output circuit coupled to the dual clocked storage element and configured to latch the data responsive to the output clock signal.
3. The apparatus of claim 1, wherein the buffer circuit comprises a plurality of dual clocked storage elements.
4. The apparatus of claim 3, wherein the data clock signal is a continuously running clock signal and the buffer circuit continuously captures data responsive to the input clock signal and continuously provides captured data responsive to the output clock signal.
5. The apparatus of claim 3, wherein the input control circuit comprises a counter, and provides the input clock signal as a plurality of one-hot signals, each one-hot signal corresponding to each of the respective dual clocked storage elements.
6. The apparatus of claim 1, further comprising a command decode circuit configured to receive the command signal, the command decode circuit physically located away from the input circuit.
7. The apparatus of claim 6, wherein the propagation delay of the command signal is longer than an operating period of the apparatus.
8. The apparatus of claim 1, further comprising a write command circuit configured to receive the delayed clock signal and the command signal and, in response, provide a write signal.
9. The apparatus of claim 8, wherein the write command circuit provides the delayed data clock signal to the output control circuit.
10. The apparatus of claim 8, wherein the command signal is a write command.
11. An integrated circuit, comprising:
a first circuit configured to receive a first input signal and a first clock signal; and
a second circuit configured to receive a second input signal and a second clock signal, and further configured to provide a third signal to the first circuit responsive to the second input signal and the second clock signal;
wherein the first circuit is further configured to capture the first input signal responsive to the first clock signal, delay the first clock signal to match a propagation delay of the third signal to the first circuit, and provide the captured first input signal responsive to the delayed clock signal.
12. The integrated circuit of claim 11, wherein the first clock signal is a data clock signal and the second clock signal is a system clock signal.
13. The integrated circuit of claim 11, wherein the first and second clock signals have the same frequency.
14. The integrated circuit of claim 11, wherein the first circuit is a write circuit, and the second circuit is a command decode circuit.
15. The integrated circuit of claim 11, wherein the third signal is a write command signal.
16. The integrated circuit of claim 11, wherein the first circuit comprises an input control circuit that generates an input clock signal responsive to the first clock signal and also comprises an output control circuit that generates an output clock signal responsive to the delayed clock signal.
17. The integrated circuit of claim 11, wherein the first circuit comprises a buffer circuit configured to receive the first input signal, the first clock signal, and the delayed clock signal.
18. The integrated circuit of claim 17, wherein the buffer comprises an input stage configured to receive the first input signal responsive to the first clock signal and an output stage configured to provide the captured first input signal responsive to the delayed clock signal.
19. The integrated circuit of claim 17, wherein the buffer comprises a dual clocked storage element configured to receive the first input signal responsive to the first clock signal and further configured to provide the captured first input signal responsive to the delayed clock signal.
20. The integrated circuit of claim 19, wherein the buffer comprises a plurality of dual clocked storage elements and the first clock signal comprises a plurality of phases, each of the dual clocked storage elements configured to receive the first input signal responsive to a respective one of the plurality of phases of the first clock signal.
21. The integrated circuit of claim 19, wherein the dual clocked storage element is a first-in-first-out circuit.
22. The integrated circuit of claim 17, wherein the first circuit comprises a plurality of buffer circuits, and each respective buffer circuit corresponds to a respective data input line of a memory.
23. A method, comprising:
capturing a first data from a first input signal line responsive to an input clock signal, the input clock signal derived from a data clock signal;
capturing a second data from a second input signal line responsive to a system clock signal;
propagating the captured second data to a circuit, the propagation of the second data to the circuit incurring a propagation delay;
delaying the data clock signal to match the propagation delay of the captured second data; and
synchronously providing the captured first data and the captured second data responsive to said delaying.
24. The method of claim 23, further comprising capturing a third data from the first input line before the captured first data is provided.
25. The method of claim 23, wherein the propagation delay includes a processing delay and a travel-time delay.
26. The method of claim 23, wherein the first data includes data to be stored in a memory array and the second data is a write command, further comprising storing the captured first data in a write bank of the memory responsive to the captured second data.
27. A method, comprising:
storing a first data in a buffer of a first circuit responsive to an input clock signal derived from a data clock signal; and
outputting the first data from the buffer responsive to an output clock signal;
wherein the output clock signal is provided by delaying the data clock signal based on a propagation delay of a third signal to the first circuit.
28. The method of claim 27, wherein the buffer synchronizes the outputted first data with the third signal.
29. The method of claim 28, further comprising outputting a write bank signal responsive to the delayed clock signal and the third signal.
30. The method of claim 27, further comprising storing a second data in the buffer responsive to the input clock signal.
31. The method of claim 27 wherein the data clock signal constantly transitions and the buffer constantly stores data and outputs data responsive thereto.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A hand held communication device comprising:
a display, said display in use have a plurality of different regions, at least one function being selectable via at least one region; and
a touch sensitive region, said touch sensitive area being arranged so that movement with respect to the touch sensitive area region causes an indicator to move across said display,
wherein said indicator is arranged to move only from one region to another.
2. A device as claimed in claim 1, wherein said touch sensitive region is arranged to detect movement of a users finger across the touch sensitive region.
3. A device as claimed in claim 1, wherein said touch sensitive region is arranged to detect movement of a tool across the touch sensitive region.
4. A device as claimed in any preceding claim, wherein said touch sensitive region comprises a surface.
5. A device as claimed in any preceding claim, wherein said touch sensitive region is a touch pad.
6. A device as claimed in any of claims 1 to 4, wherein said touch sensitive region comprises a rolling means.
7. A device as claimed in claim 6, wherein said rolling means is arranged to move said indicator in two directions about a single axis.
8. A device as claimed in claim 6, wherein said rolling means is arranged to move said indicator in a plane containing two perpendicular axis.
9. A device as claimed in any of claims 1 to 8, wherein said touch sensitive region is arranged on a first side of said device and said display is arranged on a second side.
10. A device as claimed in claim 9, wherein said first and second sides are opposite one another.
11. A device as claimed in any of claims 1 to 4, wherein said touch sensitive region is provided in conjunction with said display to provide a touch sensitive display.
12. A device as claimed in any preceding claim, wherein said indicator is a cursor.
13. A device as claimed in any preceding claim, wherein said device is a mobile telephone.
14. A method of controlling a hand held communication device comprising the steps of:
operating a touch sensitive region so as to cause an indicator to move across a display of the communication device;
controlling the indicator to move only from one region to another across the display; and
selecting a function associated the region where the indicator is located when said selection step is performed.