1. A storage cell comprising:
a plurality of logic tree circuits configured to receive an input value including a plurality of input signals and to provide a corresponding output value including a plurality of output signals in response to receiving the input value, wherein at least one of the plurality of input signals or the plurality of output signals correspond to N-Nary one-of-N signals, where N is greater than two;
wherein in response to receiving a precharge input value, the plurality of logic tree circuits is configured to output a last previous output value; and
wherein for each other input value, the plurality of logic tree circuits is configured to output a complemented input value;
wherein at least one of (1) the input value is an encoded value and in response to the plurality of input signals corresponding to N-Nary one-of-N signals, at most one signal of the input value is asserted to a logic value of one at any given time for a valid input value, and (2) the output value is an encoded value and in response to the plurality of output signals corresponding to N-Nary one-of-N signals, at most one signal of the output value is asserted to a logic value of one at any given time for a valid output value.
2. The storage cell as recited in claim 1, wherein the plurality of logic tree circuits includes one logic tree circuit for each input signal.
3. An integrated circuit comprising:
a storage cell including:
a plurality of logic tree circuits configured to receive an input value represented as a plurality of N-Nary one-of-N input signals where N is greater than two, the plurality of N-Nary input signals being implemented on a first set of physical wires;
the plurality of logic tree circuits is further configured to provide an output value represented as a plurality of output signals, the plurality of output signals being implemented on a second set of physical wires; and
wherein in response to a precharge input value the output value is unchanged, and for each other input value, the output value corresponds to a complemented input value.
4. The integrated circuit as recited in claim 3, wherein the input value is an encoded value, and at most one signal of the input value is asserted to a logic value of one at any given time for a valid input value.
5. The integrated circuit as recited in claim 4, wherein the encoding for the precharge input value has no signals at a logic value of one.
6. The integrated circuit as recited in claim 3, wherein the plurality of logic tree circuits includes one logic tree circuit for each input signal.
7. The integrated circuit as recited in claim 3, wherein each of the plurality of logic tree circuits includes:
an inverter coupled to receive a respective N-Nary one-of-N input signal;
a plurality of p-type transistors coupled in parallel between a voltage source and the inverter; and
a plurality of n-type transistors coupled in series between a circuit ground reference and a respective one of the plurality of N-Nary one-of-N output signals.
8. The integrated circuit as recited in claim 7, wherein the plurality of p-type transistors includes one p-type transistor for each of the output signals minus one.
9. The integrated circuit as recited in claim 7, wherein the plurality of n-type transistors includes one n-type transistor for each of the output signals minus one.
10. The integrated circuit as recited in claim 3, further comprising a plurality of inverter gates, each coupled to a respective logic tree circuit output and configured to provide an inverted output signal.
11. An integrated circuit comprising:
a storage cell including:
a plurality of logic tree circuits configured to receive an input value represented as a plurality of input signals, the plurality of input signals being implemented on a first set of physical wires;
the plurality of logic tree circuits is further configured to provide an output value represented as a plurality of N-Nary one-of-N output signals, where N is greater than 2, the plurality of N-Nary one-of-N output signals being implemented on a second set of physical wires; and
wherein in response to a precharge input value the output value is unchanged, and for each other input value, the output value corresponds to a complemented input value.
12. The integrated circuit as recited in claim 11, wherein the output value is an encoded value, and at most one signal of the output value is asserted to a logic value of one at any given time for a valid output value.
13. The integrated circuit as recited in claim 11, wherein the plurality of logic tree circuits includes one logic tree circuit for each input signal.
14. The integrated circuit as recited in claim 11, wherein each of the plurality of logic tree circuits includes:
an inverter coupled to receive a respective input signal;
a plurality of p-type transistors coupled in series between a voltage source and a respective one of the plurality of output signals; and
a plurality of n-type transistors coupled in parallel between a circuit ground reference and the inverter.
15. The integrated circuit as recited in claim 11, further comprising a plurality of inverter gates, each coupled to a respective logic tree circuit input and configured to provide an inverted input signal.
16. The integrated circuit as recited in claim 11, wherein the input value is an encoded value having at most one signal at a logic value of zero at any given time.
17. The integrated circuit as recited in claim 16, wherein the encoding for the precharge input value has no signals at a logic value of zero.
18. A storage cell comprising:
a plurality of logic tree circuits configured to receive a plurality of input values, wherein each input value includes a plurality of input signals;
wherein the plurality of logic tree circuits is further configured to provide a corresponding plurality of output values in response to receiving the input values, wherein each output value includes a plurality of N-Nary one-of-N output signals, where N is greater than two;
wherein each of the plurality of logic tree circuits is configured to receive a respective input signal and to provide a corresponding respective N-Nary one-of-N output signal;
wherein in response to receiving a precharge input value, the output value remains a previous output value, and for each other input value, the output value corresponds to a complemented input value;
wherein at least one of (1) the input value is an encoded value and in response to the plurality of input signals corresponding to N-Nary one-of-N signals, at most one signal of the input value is asserted to a logic value of one at any given time for a valid input value, and (2) the output value is an encoded value and in response to the plurality of output signals corresponding to N-Nary one-of-N signals, at most one signal of the output value is asserted to a logic value of one at any given time for a valid output value.
19. The storage cell as recited in claim 18, wherein the plurality of logic tree circuits includes one logic tree circuit for each input signal.
20. A storage cell comprising:
a plurality of logic tree circuits configured to receive a plurality of input values, wherein each input value includes a plurality of input signals;
wherein the plurality of logic tree circuits is further configured to provide a corresponding plurality of output values in response to receiving the input values, wherein each output value includes a plurality of N-Nary one-of-N output signals, where N is greater than two
wherein each of the plurality of logic tree circuits is configured to receive a respective input signal and to provide a corresponding respective N-Nary one-of-N output signal;
wherein in response to receiving a precharge input value, the output value remains a previous output value, and for each other input value, the output value corresponds to a complemented input value;
wherein each of the plurality of logic tree circuits includes:
an inverter coupled to receive a respective input signal;
a plurality of p-type transistors coupled in series between a voltage source and a respective one of the plurality of output signals; and
a plurality of n-type transistors coupled in parallel between a circuit ground reference and the inverter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A process for preparing aryllithium compounds of the formulae (IV) and (VI) comprising the steps of
a. reacting at least one halogen compound (I) with lithium metal to form a lithium compound of the formula (II)
b. reacting the lithium compound of formula (II) with aromatic compounds of the formulae (III) andor (V) to deprotonate the aromatic compounds of formulae (III) andor (V) and form lithium aromatics of formulae (IV) andor (VI), wherein the steps a) and b) are carried out as a one-pot reaction,
where R is methyl, a primary, secondary or tertiary alkyl radical having from 2 to 12 carbon atoms, alkyl substituted by a radical selected from the group consisting of phenyl, substituted phenyl, aryl, heteroaryl, alkoxy, dialkylamino, alkylthio and substituted or unsubstituted cycloalkyl having from 3 to 8 carbon atoms,
Hal=fluorine, chlorine, bromine or iodine,
X1-4 are, independently of one another, each carbon or two adjacent radicals X1-4R1-4 can together be O, or S;
the radicals R1-4 and the radical Z are substituents selected from the group consisting of hydrogen, methyl, primary, secondary or tertiary, cyclic or acyclic alkyl radicals having from 2 to 12 carbon atoms, substituted cyclic or acyclic alkyl groups, alkoxy, dialkylamino, alkylamino, arylamino, diarylamino, phenyl, substituted phenyl, alkylthio, diarylphosphino, dialkyiphosphino, dialkylaminocarbonyl or diarylaminocarbonyl, monoalkylaminocarbonyl or monoarylaminocarbonyl, CO2\u2212, hydroxyalkyl, alkoxyalkyl, fluorine and chlorine, CN and heteroaryl or two adyacent radicals R1-4 form an aromatic or aliphatic ring.
2. The process as claimed in claim 1, wherein the process is carried out at temperatures in the range from \u2212100 to +25\xb0 C.
3. The process as claimed in claim 1, wherein the amount of lithium to be added per mole of halogen to be reacted is in the range from 1.95 to 2.5 mol.
4. The process as claimed claim 1, wherein the process is carried out in an ether solvent.
5. The process as claimed in claim 1, said process further comprising adding organic redox systems to the reaction of the Li metal in step a).
6. The process as claimed in claim 1, wherein the compounds of the formula (III) or (V) include an alkoxy, F, Cl, substituted amino, CN, heteroaryl, aminoalkyl or hydroxyalkyl radical in the ortho position relative to the deprotonating hydrogen.
7. The process as claimed in claim 1, further comprising the step of reacting the compounds of the formulae (IV) andor (VI) with an electrophile.
8. The process as claimed in claim 7, wherein the reaction with the electrophile is carried out either after production of the lithiated compound (IV) andor (V) or in a one-pot process by simultaneous addition to the reaction mixture.
9. The process as claimed in claim 7, wherein the electrophile is selected from the group consisting of carbon, boron or silicon compounds.
10. The process as claimed in claim 1, wherein two adjacent radicals R1-4 form an aromatic or aliphatic ring.
11. A process as claimed in claim 1, wherein the lithium compound of the formula (II) is present in a concentration ranging from 5 to 30% by weight.
12. A process for preparing aryllithium compounds of the formula (IV) and (VI) comprising the steps of
a. reacting at least one halogen compound (I) with lithium metal to form a lithium compound of the formula (II)
b. reacting the lithium compound of formula (II) with aromatic compounds of the formula (III) andor (V) to deprotonate the aromatic compounds of formula (III) andor (V) and form lithium aromatics of formula (IV) andor (VI).
where R is methyl, a primary, secondary or tertiary alkyl radical having from 2 to 12 carbon atoms, alkyl substituted by a radical selected from the group consisting of phenyl, substituted phenyl, aryl, heteroaryl, alkoxy, dialkylamino, alkylthio and substituted or unsubstituted cycloakyl having from 3 to 8 carbon atoms,
Hal=fluorine, chlorine, bromine or iodine,
X1-4 are, independently of one another, each carbon or two adjacent radicals X1-4R1-4 can together be O, or S;
the radicals R1-4 and the radical Z are substituents selected from the group consisting of hydrogen, methyl, primary, secondary or tertiary, cyclic or acyclic alkyl radicals having from 2 to 12 carbon atoms, substituted cyclic or acyclic alkyl groups, alkoxy, dialkylamino, alkylamino, arylamino, diarylamino, phenyl, substituted phenyl, alkylthio, diarylphosphino, dialkylphosphino, dialkylaminocarbonyl or diarylaminocarbonyl, monoalkylaminocarbonyl or monoarylaminocarbonyl, CO2\u2212, hydroxyalkyl, alkoxyalkyl, fluorine and chlorine, CN and heteroaryl, or two adjacent radicals R1-4 form an aromatic or aliphatic ring,
wherein (I) the process is carried out at temperatures in the range from \u2212100 to \u221225\xb0 C. and (II) the process is carried out in an ether solvent.