1. A fungicidal composition comprising the components
(i) at least one quaternary ammonium compound;
(ii) a copolymer latex containing a nonionic surfactant;
(iii) a UV absorber; and
(iv) water.
2. The composition of claim 1 wherein component (i) is selected from the group consisting of dialkyl dimethyl ammonium salts and alkylbenzyl dimethyl ammonium salts; component (ii) is a vinyl acetateoctyl maleate copolymer containing the nonionic surfactant octylphenyl ethoxylate; and component (iii) is selected from the group consisting of zinc oxide and titanium dioxide.
3. The composition of claim 2 wherein component (i) is selected from the group consisting of dialkyl dimethyl ammonium chloride, alkylbenzyl dimethyl ammonium chloride and mixtures thereof; component (ii) contains from about 0.5 to about 1.0 wt % of said nonionic surfactant; and component (iii) is titanium dioxide having a mean particle diameter of about 0.5 micron.
4. The composition of claim 3 wherein component (i) is didecyl dimethyl chloride.
5. The composition of claim 4 wherein the components are present in the following weight percentages:
component (i) from about 0.5 to about 25 wt %;
component (ii) from about 1.0 to about 40 wt %; and
component (iii) from about 0.5 to about 12 wt %.
6. The composition of claim 5 including a further component (v) of an aqueous emulsion comprising hydroxyl-terminated dimethyl siloxane, amorphous silica and aminomethylpropanol, said component (v) being present in an amount of from about 0 to about 20 wt %.
7. The composition of claim 6 wherein the components are present in the following approximate weight percentages:
component (i) about 12 wt %;
component (ii) about 36 wt %;
component (iii) from about 4 to about 6 wt %; and
component (v) from about 5 to about 7 wt %.
8. The composition of claim 7 diluted with water.
9. The composition of claim 8 wherein the dilution is with from about 10 to about 15 parts water.
10. The composition of claim 9 wherein the dilution is with about 12 parts water.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing, comprising:
forming a first guard trace on a first layer of a circuit board and offset laterally from a first signal trace but at least partially overlapping a second signal trace in a second layer of the circuit board; and
forming a second guard trace on the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace.
2. The method of claim 1, comprising electrically coupling the first and second guard traces.
3. The method of claim 2, wherein the electrically coupling comprises forming a first conductor coupled between the first and second guard traces and a second conductor coupled between the first and second guard traces and spaced a distance from the first conductor.
4. The method of claim 3, wherein the first and second signal traces are operable to convey signals at a minimum wavelength and the distance is less than or equal to one quarter of the minimum wavelength.
5. The method of claim 1, wherein the circuit board comprises a multilayer semiconductor chip package substrate.
6. The method of claim 5, wherein the multilayer semiconductor chip package substrate comprises a core with first and second sides and at least one buildup layer on each of the first and second sides.
7. The method of claim 1, comprising coupling a semiconductor chip to the circuit board.
8. The method of claim 1, comprising electrically coupling a memory device to at least one of the first and second signal traces.
9. The method of claim 1, comprising forming power conductor on the circuit board.
10. The method of claim 1, comprising coupling the circuit board to an electronic device.
11. The method of claim 1, comprising forming a third signal trace adjacent to the first signal trace and between the first guard trace and the first signal trace.
12. The method of claim 1, wherein the method is performed by executing instructions stored in a computer readable medium.
13. A method of reducing crosstalk in a circuit board, comprising:
using a first guard trace associated with a first layer of the circuit board and offset laterally from the first signal trace but at least partially overlapping a second signal trace associated with a second layer of the circuit board and a second guard trace associated with the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace to reduce crosstalk between the first and second signal traces.
14. The method of claim 13, wherein the first and second guard traces are electrically coupled.
15. The method of claim 14, wherein the first and second guard traces are electrically coupled by a first conductor coupled between the first and second guard traces and a second conductor coupled between the first and second guard traces and spaced a distance from the first conductor.
16. The method of claim 15, wherein the first and second signal traces are operable to convey signals at a minimum wavelength and the distance is less than or equal to one quarter of the minimum wavelength.
17. The method of claim 13, wherein the circuit board comprises a multilayer semiconductor chip package substrate.
18. The method of claim 17, wherein the multilayer semiconductor chip package substrate comprises a core with first and second sides and at least one buildup layer on each of the first and second sides.
19. The method of claim 13, wherein the circuit board comprises a semiconductor chip.
20. The method of claim 19, comprising operating the semiconductor chip to drive signals through at least one of the first and second signal traces.
21. The method of claim 13, wherein the circuit board comprises a memory device electrically coupled to at least one of the first and second signal traces.
22. The method of claim 13, comprising using a third signal trace associated with the first layer and positioned adjacent to the first signal trace to convey signals.
23. A circuit board, comprising:
a first signal trace associated with a first layer of the circuit board;
a second signal trace associated with a second layer of the circuit board;
a first guard trace associated with the first layer and offset laterally from the first signal trace but at least partially overlapping the second signal trace; and
a second guard trace associated with the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace.
24. The apparatus of claim 23, wherein the first and second guard traces are electrically coupled.
25. The apparatus of claim 24, wherein the first and second guard traces are electrically coupled by a first conductor coupled between the first and second guard traces and a second conductor coupled between the first and second guard traces and spaced a distance from the first conductor.
26. The apparatus of claim 25, wherein the first and second signal traces are operable to convey signals at a minimum wavelength and the distance is less than or equal to one quarter of the minimum wavelength.
27. The apparatus of claim 23, wherein the circuit board comprises a multilayer semiconductor chip package substrate.
28. The apparatus of claim 27, wherein the multilayer semiconductor chip package substrate comprises a core with first and second sides and at least one buildup layer on each of the first and second sides.
29. The apparatus of claim 23, comprising a semiconductor chip coupled to the circuit board.
30. The apparatus of claim 23, comprising a memory device electrically coupled to at least one of the first and second signal traces.
31. The apparatus of claim 23, comprising an electronic device coupled to the circuit board.
32. The apparatus of claim 23, comprising a third signal associated with the first layer of the circuit board and positioned adjacent to the first signal trace and between the first guard trace and the first signal trace.