What is claimed is:
1. A semiconductor memory device for storing data comprising:
a data output circuit for receiving and outputting the stored data;
a mask signal input circuit connected to the data output circuit for receiving a mask signal used to mask the data output from the data output circuit and providing the mask signal to the data output circuit; and
an input control circuit connected to the mask signal input circuit for generating an activation signal that activates the mask signal input circuit and providing the activation signal to the mask signal input circuit, wherein the input control circuit generates the activation signal based on at least one of a plurality of mode setting signals and a latency determination signal, the mode setting signal being used to activate the mask signal input circuit and selectively set one of a plurality of operation modes of the semiconductor memory device, and the latency determination signal having a level corresponding to latency information.
2. The semiconductor memory device according to claim 1, wherein the latency information includes CAS latency and mask latency.
3. The semiconductor memory device according to claim 2, wherein the plurality of operation modes include an idle mode for decreasing power consumption, and the input control circuit provides the activation signal to the mask signal input circuit during the idle mode when the latency determination signal indicates that the CAS latency has a value smaller than that of the mask latency.
4. The semiconductor memory device according to claim 2, wherein the plurality of mode setting signals include a power down signal and an active signal, and the plurality of operation modes include a power down mode set by the power down signal, an active mode set by the active signal, and an idle mode for decreasing power consumption, and wherein the input control circuit stops providing the activation signal to the mask signal input circuit during the power down mode based on the mode setting signals, provides the activation signal to the mask signal input circuit during the active mode based on the mode setting signals, and provides the activation signal to the mask signal input circuit during the idle mode based on the latency determination signal.
5. The semiconductor memory device according to claim 4, wherein the input control circuit provides the activation signal to the mask signal input circuit during the idle mode when the latency determination signal indicates that the CAS latency has a value smaller than that of the mask latency.
6. A semiconductor memory device for storing data comprising:
a data input circuit for receiving the data;
a mask signal input circuit connected to the data input circuit for receiving a mask signal used to mask the data and providing the mask signal to the data input circuit; and
an input control circuit connected to the mask signal input circuit for generating an activation signal that activates the mask signal input circuit and providing the activation signal to the mask signal input circuit, wherein the input control circuit generates the activation signal based on at least one of a plurality of mode setting signals and a latency determination signal, the mode setting signal being used to activate the mask signal input circuit and selectively set one of a plurality of operation modes of the semiconductor memory device, and the latency determination signal having a level corresponding to latency information.
7. A synchronous memory for storing data and reading stored data based on a clock signal comprising:
a data output circuit for receiving and outputting the stored data based on the clock signal;
a mask signal input circuit connected to the data output circuit for receiving a mask signal used to mask the data output from the data output circuit and providing the mask signal to the data output circuit; and
an input control circuit connected to the mask signal input circuit for generating an activation signal that activates the mask signal input circuit and providing the activation signal to the mask signal input circuit, wherein the input control circuit generates the activation signal based on at least one of a plurality of mode setting signals and a latency determination signal, the mode setting signal being used to activate the mask signal input circuit and selectively set one of a plurality of operation modes of the synchronous memory, and the latency determination signal having a level corresponding to latency information.
8. The synchronous memory according to claim 7, wherein the latency information includes CAS latency and mask latency.
9. The synchronous memory according to claim 8, wherein the plurality of operation modes includes an idle mode for decreasing power consumption, and the input control circuit provides the activation signal to the mask signal input circuit during the idle mode when the latency determination signal indicates that the CAS latency has a value smaller than that of the mask latency.
10. The synchronous memory according to claim 8, wherein the plurality of mode setting signals include a power down signal and an active signal, and the plurality of operation modes include a power down mode set by the power down signal, an active mode set by the active signal, and an idle mode for decreasing power consumption, and wherein the input control circuit stops providing the activation signal to the mask signal input circuit during the power down mode based on the mode setting signals, provides the activation signal to the mask signal input circuit during the active mode based on the mode setting signals, and provides the activation signal to the mask signal input circuit during the idle mode based on the latency determination signal.
11. The synchronous memory according to claim 10, wherein the input control circuit provides the activation signal to the mask signal input circuit during the idle mode when the latency determination signal indicates that the CAS latency has a value smaller than that of the mask latency.
12. The synchronous memory according to claim 11, wherein the input control circuit includes a switching circuit for generating a switching signal based on a logic operation performed with the active signal and the latency determination signal, and generates the activation signal based on a logic operation performed with the switching signal and the power down signal.
13. A synchronous memory for storing data and reading stored data based on a clock signal comprising:
a data input circuit for receiving the data;
a mask signal input circuit connected to the data input circuit for receiving a mask signal used to mask the data and providing the mask signal to the data input circuit; and
an input control circuit connected to the mask signal input circuit for generating an activation signal that activates the mask signal input circuit and providing the activation signal to the mask signal input circuit, wherein the input control circuit generates the activation signal based on at least one of a plurality of mode setting signals and a latency determination signal, the mode setting signal being used to activate the mask signal input circuit and selectively set one of a plurality of operation modes of the synchronous memory, and the latency determination signal having a level corresponding to latency information.
14. A semiconductor memory device comprising:
a data mask signal input circuit receiving a data mask signal;
an input control circuit for outputting an activation signal to the data mask signal input circuit in response to an operation mode signal and a latency signal.
15. The semiconductor memory device according to claim 1, wherein the plurality of operation modes include an idle mode, and the mask signal input circuit is activated during the idle mode when a value of the latency information corresponds to 1.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1.-30. (canceled)
31. A device, comprising:
a photodiode configured to convert a first modulated form of a downstream optical signal into an electrical signal;
a modulator configured to modulate an unmodulated form of the downstream optical signal to produce a second modulated form of the downstream optical signal; and
a wavelength shifter configured to adjust a wavelength of the second modulated form of the downstream optical signal to produce an upstream optical signal.
32. The device of claim 31, further comprising:
a circulator configured to facilitate reception of the downstream optical signal and transmission of the upstream optical signal over the same optical fiber.
33. The device of claim 31, further comprising:
an optical power splitter configured to direct the first modulated form of the downstream optical signal to the photodiode and the unmodulated form of the downstream optical signal to the modulator.
34. The device of claim 33, further comprising:
an optical amplifier coupled to the optical power splitter, wherein the optical amplifier is configured to amplify the unmodulated form of the downstream optical signal.
35. The device of claim 31, further comprising:
a noise reduction filter configured to filter noise from the upstream optical signal.
36. The device of claim 31, wherein the device is configured to receive the unmodulated form of the downstream optical signal during a time slot, and wherein the modulator is configured to modulate the unmodulated form of the downstream optical signal for a portion of the time slot, wherein the portion is less than a length of the time slot.
37. The device of claim 31, wherein the device is a subscriber device configured to convey the upstream optical signal to a headend within an optical network.
38. The device of claim 31, wherein the photodiode is a tunable photodiode.
39. An optical system, comprising:
a subscriber device configured to:
convert a first modulated form of a downstream optical signal into an electrical signal;
modulate an unmodulated form of the downstream optical signal to produce a second modulated form of the downstream optical signal; and
adjust a wavelength of the second modulated form of the downstream optical signal to produce an upstream optical signal.
40. The optical system of claim 39, wherein the subscriber device is configured to receive the downstream optical signal and transmit the upstream optical signal over the same optical fiber.
41. The optical system of claim 39, wherein the subscriber device includes an optical power splitter configured to direct the modulated form of the downstream optical signal to a photodiode of the subscriber device and the unmodulated form of the downstream optical signal to a modulator of the subscriber device.
42. The optical system of claim 39, wherein the subscriber device includes a noise reduction filter configured to filter noise from the upstream optical signal.
43. The optical system of claim 39, wherein the subscriber device is configured to:
receive the first modulated form of the downstream optical signal during a first time slot;
and receive the unmodulated form of the downstream optical signal during a second time slot distinct from the first time slot.
44. The optical system of claim 39, further comprising:
a headend configured to communicate with the subscriber device.
45. A method, comprising:
converting, at a photodiode of a communication device, a first modulated form of a downstream optical signal into an electrical signal;
modulating, by the communication device, an unmodulated form of the downstream optical signal to produce a second modulated form of the downstream optical signal; and
adjusting, by the communication device, a wavelength of the second modulated form of the downstream optical signal to produce an upstream optical signal.
46. The method of claim 45, further comprising:
the communication device receiving the downstream optical signal over an optical fiber; and
the communication device transmitting the upstream optical signal over the optical fiber.
47. The method of claim 46, further comprising:
the communication device applying a noise reduction filter to the upstream optical signal prior to transmitting the upstream optical signal.
48. The method of claim 46, further comprising:
the communication device receiving the first modulated form of the downstream optical signal during a first time slot; and
the communication device receiving the unmodulated form of the downstream optical signal during a second time slot distinct from the first time slot.
49. The method of claim 45, further comprising:
the communication device amplifying, via an optical amplifier, the unmodulated form of the downstream optical signal.
50. The method of claim 45, wherein the communication device is a subscriber device in an optical network.