1. A method comprising:
applying logic operations to first and second differential pairs of periodic logic signals having a local frequency and to delayed versions thereof to produce a first differential pair of reference signals having relatively high spectral content at three times said local frequency and relatively low spectral content at other frequencies; and
mixing a differential pair of first input signals with said first differential pair of reference signals to produce a differential pair of first output signals having a dominant spectral component at three times said local frequency less a center frequency of said first input signals.
2. The method of claim 1, wherein applying said logic operations also produces a second differential pair of reference signals that is a delayed version of said first differential pair of reference signals, and said method further comprises:
mixing a differential pair of second input signals with said second differential pair of reference signals to produce a differential pair of second output signals having a dominant spectral component at three times said local frequency less a center frequency of said second input signals.
3. The method of claim 1,
wherein said first input signals are radio frequency signals and mixing said differential pair of first input signals with said first differential pair of reference signals includes down converting said input signals.
4. The method of claim 1,
wherein said first output signals are radio frequency signals and mixing said differential pair of first input signals with said first differential pair of reference signals includes up converting said input signals.
5. The method of claim 1,
wherein applying said logic operations includes applying said logic operations to produce said first differential pair of reference signals having a periodic pattern of three portions at a logic value interlaced with three portions at a different logic value.
6. The method of claim 1, further comprising:
generating said second differential pair of periodic logic signals with a phase delay of 90\xb0 relative to said first differential pair of periodic logic signals;
generating a delayed version of said first differential pair of periodic logic signals with a phase delay of 45\xb0 relative to said first differential pair of periodic logic signals; and
generating a delayed version of said second differential pair of periodic logic signals with a phase delay of 45\xb0 relative to said second differential pair of periodic logic signals.
7. The method of claim 1, further comprising:
generating first and second differential pairs of substantially sinusoidal local oscillator signals; and
shaping said first and second differential pairs of local oscillator signals and delayed versions thereof to produce said first and second differential pairs of periodic logic signals and delayed versions thereof.
8. The method of claim 7, wherein generating said first and second differential pairs of substantially sinusoidal local oscillator signals includes generating said second differential pair of local oscillator signals with a phase delay of 90\xb0 relative to said first differential pair of local oscillator signals, and said method further comprises:
generating a delayed version of said first differential pair of periodic local oscillator signals with a phase delay of 45\xb0 relative to said first differential pair of periodic local oscillator signals; and
generating a delayed version of said second differential pair of periodic local oscillator signals with a phase delay of 45\xb0 relative to said second differential pair of periodic local oscillator signals.
9. A method comprising:
mixing first and second differential pairs of local oscillator signals having a local frequency and a relatively low spectral content at three times said local frequency with a differential pair of input signals to produce a differential pair of output signals having a relatively high spectral content at three times said local frequency less a center frequency of said input signals.
10. The method of claim 9,
wherein said input signals are radio frequency signals and mixing said differential pair of input signals with said first and second differential pairs of local oscillator signals includes down converting said input signals.
11. The method of claim 9,
wherein said output signals are radio frequency signals and mixing said differential pair of input signals with said first and second differential pairs of local oscillator signals includes up converting said input signals.
12. The method of claim 9, further comprising:
generating said first and second differential pairs of local oscillator signals as substantially sinusoidal signals such that said second differential pair of local oscillator signals has a phase difference relative to said first differential pair of local oscillator signals, wherein an absolute value of said phase difference is substantially 90\xb0.
13. The method of claim 12, wherein mixing said first differential pair of local oscillator signals with said differential pair of input signals further comprises:
generating a differential pair of mixer signals having half said phase difference relative to said first differential pair of local oscillator signals.
14. A method comprising:
mixing first, second and third differential pairs of local oscillator signals having a local frequency and relatively low spectral content at three times said local frequency with a differential pair of input signals to produce a differential pair of output signals having a relatively high spectral content at three times said local frequency less a center frequency of said input signals.
15. The method of claim 14,
wherein said input signals are radio frequency signals and mixing said differential pair of input signals with said first, second and third differential pairs of local oscillator signals includes down converting said input signals.
16. The method of claim 14,
wherein said output signals are radio frequency signals and mixing said differential pair of input signals with said first, second and third differential pairs of local oscillator signals includes up converting said input signals.
17. The method of claim 14, further comprising:
generating said first, second and third differential pairs of local oscillator signals as substantially sinusoidal signals such that said third differential pair of local oscillator signals has a phase difference relative to said first differential pair of local oscillator signals, wherein an absolute value of said phase difference is substantially 120\xb0, and said second differential pair of local oscillator signals has half said phase difference relative to said first differential pair of local oscillator signals.
18. An integrated circuit comprising:
a logic circuit to apply logic operations to first and second differential pairs of periodic logic signals having a local frequency and to delayed versions thereof to produce a first differential pair of reference signals having relatively high spectral content at three times said local frequency and relatively low spectral content at other frequencies; and
a first mixer to mix a differential pair of first input signals with said first differential pair of reference signals to produce a differential pair of first output signals having a dominant spectral component at three times said local frequency less a center frequency of said first input signals.
19. The integrated circuit of claim 18, wherein said logic circuit is to produce a second differential pair of reference signals that is a delayed version of said first differential pair of reference signals, and the integrated circuit further comprises:
a second mixer to mix a differential pair of second input signals with said second differential pair of reference signals to produce a differential pair of second output signals having a dominant spectral component at three times said local frequency less a center frequency of said second input signals.
20. The integrated circuit of claim 18, further comprising:
a local oscillator to generate first and second differential pairs of substantially sinusoidal local oscillator signals; and
signal shapers to shape said first and second differential pairs of local oscillator signals and delayed versions thereof to produce said first and second differential pairs of periodic logic signals and delayed versions thereof.
21. An integrated circuit comprising:
a Gilbert cell active mixer having four branches and having three or more serially-connected transistors in each of said four branches.
22. The integrated circuit of claim 21, wherein said mixer further includes:
a first differential pair of input terminals to receive a first differential pair of local oscillator signals;
a second differential pair of input terminals to receive a second differential pair of local oscillator signals having a phase difference relative to said first differential pair of local oscillator signals, wherein an absolute value of said phase difference is substantially 90\xb0; and
passive elements coupled to said transistors and to said first and second differential pairs of input terminals to generate a differential pair of mixer signals having a phase difference of substantially 45\xb0 from both of said differential pairs of local oscillator signals.
23. The integrated circuit of claim 22, wherein said passive elements are resistive elements.
24. The integrated circuit of claim 22, wherein said passive elements are capacitive elements.
25. An integrated circuit comprising:
a quad-ring passive resistive mixer having four branches and having three or more serially-connected transistors in each of said four branches.
26. The integrated circuit of claim 25, wherein said transistors are field effect transistors.
27. The integrated circuit of claim 25, wherein said mixer further comprises:
a differential pair of input terminals;
a differential pair of output terminals;
a first node coupling a first and a second of said branches, and a second node coupling a third and a fourth of said branches, said first and second nodes connected to said differential pair of input terminals; and
a third node coupling said first and fourth branches, and a fourth node coupling said second and third branches, said third and fourth nodes connected to said differential pair of output terminals.
28. The integrated circuit of claim 25, wherein said mixer further comprises:
a first differential pair of reference input terminals to receive a first differential pair of local oscillator signals;
a second differential pair of reference input terminals to receive a second differential pair of local oscillator signals having a phase difference relative to said first differential pair of local oscillator signals, wherein an absolute value of said phase difference is substantially 1200; and
a third differential pair of reference input terminals to receive a third differential pair of local oscillator signals having half said phase difference relative to said first differential pair of local oscillator signals,
wherein gates of transistors in said first and third of said branches are connected to negative terminals of said reference input terminals, and gates of transistors in said second and fourth of said branches are connected to positive terminals of said reference input terminals.
29. A communication device comprising:
a monopole antenna; and
an integrated circuit coupled to said antenna, said integrated circuit including at least:
a logic circuit to apply logic operations to first and second differential pairs of periodic logic signals having a local frequency and to delayed versions thereof to produce a first differential pair of reference signals having relatively high spectral content at three times said local frequency and relatively low spectral content at other frequencies; and
a first mixer to mix a differential pair of first input signals with said first differential pair of reference signals to produce a differential pair of first output signals having a dominant spectral component at three times said local frequency less a center frequency of said first input signals.
30. The communication device of claim 29, wherein said logic circuit is to produce a second differential pair of reference signals that is a delayed version of said first differential pair of reference signals, and said integrated circuit further comprises:
a second mixer to mix a differential pair of second input signals with said second differential pair of reference signals to produce a differential pair of second output signals having a dominant spectral component at three times said local frequency less a center frequency of said second input signals.
31. The communication device of claim 29, wherein said integrated circuit further comprises:
a local oscillator to generate first and second differential pairs of substantially sinusoidal local oscillator signals; and
signal shapers to shape said first and second differential pairs of local oscillator signals and delayed versions thereof to produce said first and second differential pairs of periodic logic signals and delayed versions thereof.
32. A communication device comprising:
a monopole antenna; and
an integrated circuit coupled to said antenna, said integrated circuit including at least:
a Gilbert cell active mixer having four branches and having three or more serially-connected transistors in each of said four branches.
33. The communication device of claim 32, wherein said mixer further includes:
a first differential pair of input terminals to receive a first differential pair of local oscillator signals;
a second differential pair of input terminals to receive a second differential pair of local oscillator signals having a phase difference relative to said first differential pair of local oscillator signals, wherein an absolute value of said phase difference is substantially 90\xb0; and
passive elements coupled to said transistors and to said first and second differential pairs of input terminals to generate a differential pair of mixer signals having a phase difference of substantially 45\xb0 from both of said differential pairs of local oscillator signals.
34. The communication device of claim 33, wherein said passive elements are resistive elements.
35. The communication device of claim 33, wherein said passive elements are capacitive elements.
36. A communication device comprising:
a monopole antenna; and
an integrated circuit coupled to said antenna, said integrated circuit including at least:
a quad-ring passive resistive mixer having four branches and having three or more serially-connected transistors in each of said four branches.
37. The communication device of claim 36, wherein said transistors are field effect transistors.
38. The communication device of claim 36, wherein said mixer further comprises:
a differential pair of input terminals;
a differential pair of output terminals;
a first node coupling a first and a second of said branches, and a second node coupling a third and a fourth of said branches, said first and second nodes connected to said differential pair of input terminals; and
a third node coupling said first and fourth branches, and a fourth node coupling said second and third branches, said third and fourth nodes connected to said differential pair of output terminals.
39. The communication device of claim 36, wherein said mixer further comprises:
a first differential pair of reference input terminals to receive a first differential pair of local oscillator signals;
a second differential pair of reference input terminals to receive a second differential pair of local oscillator signals having a phase difference relative to said first differential pair of local oscillator signals, wherein an absolute value of said phase difference is substantially 120\xb0; and
a third differential pair of reference input terminals to receive a third differential pair of local oscillator signals having half said phase difference relative to said first differential pair of local oscillator signals,
wherein gates of transistors in said first and third of said branches are connected to negative terminals of said reference input terminals, and gates of transistors in said second and fourth of said branches are connected to positive terminals of said reference input terminals.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for managing low memory in a first computer device having a processor for executing an operating system and an application, and a memory available to the operating system and application, wherein the first computer device is an interface for exchanging electronic messages with mobile devices in a wireless network, including steps of:
(a) reserving within a block of memory a first reserve buffer and a second reserve buffer for the application that are unavailable to the application until released;
(b) releasing the first reserve buffer for use by the application upon determining that memory use by the application has reached a first threshold;
(c) generating a first alert after determining that the memory use has reached the first threshold, and sending the first alert, once generated over a network from the first computer device to another computer device;
(d) upon detecting the first alert, causing electronic messages to be rerouted away from the first computer device and to at least one further computer device that is connected to a common network as the first computer device;
(e) determining if memory use by the application exceeds a second threshold after the first reserve buffer is released and if so releasing the second reserve buffer for use by the application and issuing a second alert; and
(f) upon detecting the second alert, commencing an automated application shutdown routine including storing selected information from the block of memory to a persistent storage.
2. The method of claim 1 including storing selected information from the block of memory to the persistent storage subsequent to determining that the memory use has reached the threshold.
3. The method of claim 1 wherein in step (b) a determination is made that the memory use has exceeded the first threshold when an out-of-memory exception is generated by the operating system in respect of the application, and in (e) a determination is made that the memory use has exceeded the second threshold when a second out-of-memory exception is generated by the operating system in respect of the application while the first reserve buffer is released.
4. The method of claim 1 wherein the size of the second reserve buffer is less than that of the first reserve buffer.
5. The method of claim 1, including after step (b), re-reserving within the block of memory the first reserve buffer if the memory use by the application falls below a threshold.
6. The method of claim 1 wherein the first computer device stores in the block of memory outgoing electronic messages that are to be sent over the wireless network to the mobile devices, wherein storing selected information from the block of memory to the persistent storage comprises storing at least some of the stored outgoing electronic messages in the persistent storage.
7. The method of claim 6 wherein the stored outgoing electronic messages stored in the block of memory include critical messages that are required to be sent to selected mobile devices in order to avoid leaving the selected mobile devices with incorrect or ambiguous information as to the status of electronic messages sent therefrom, and the step of storing at least some of the stored outgoing messages in a persistent storage comprises selecting from among the stored outgoing electronic messages the critical messages that are required to be sent to wireless mobile devices, and attempting to store the selected critical messages in the persistent storage.
8. The method of claim 1 wherein the block of memory is booked for the application upon start up of the application and the first and second reserve buffers reserved therein upon start up of the application.
9. A system for managing memory on a first computer device that is an interface for exchanging electronic messages with mobile devices in a wireless network, the first computer device having a processor, a memory, an operating system and an application, and comprising a low memory manager for reserving within a block of memory a first reserve buffers that is unavailable to the application until released by the low memory manager; and releasing the first reserve buffer for use by the application upon detecting a first out of memory exception generated by the operating system in respect of the application; wherein the first computer device stores in the memory outgoing electronic messages that are to be sent over the wireless network to wireless mobile devices;
the low memory manager being configured for reserving within the block of memory, in addition to the first reserve buffer, a second reserve buffer that is unavailable to the application until released by the low memory manager, generating a first alert after detecting the first out of memory exception generated by the operating system in respect of the application and generating a second alert and releasing the second reserve buffer for use by the application upon detecting a further out of memory exception generated by the operating system in respect of the application;
a shutdown manager for storing at least some of the stored outgoing electronic messages data from the block of memory to a persistent storage subsequent to detecting the second alert; and
another computer device for receiving the warning signal over a network and causing electronic messages to be rerouted away from the first computer device and to at least one further computer device that is connected to a common network as the first computer device.
10. The system of claim 9 wherein the second reserve buffer is released only if the first reserve buffer is still released when the further out of memory exception is generated.