1. A method for handling retransmission and acknowledgements of data packets transmitted from a sender to a recipient over a network, the method comprising:
receiving data packets from the sender;
transmitting the received data packets downstream to the recipient;
pre-acknowledging the received data packets by sending acknowledgments to the sender before receiving acknowledgements from a downstream entity for the data packets; and
controlling the flow of data packets received from the sender.
2. The method of claim 1, further comprising:
retaining a copy of the transmitted data packets until acknowledged as received from a downstream entity.
3. The method of claim 1, wherein each data packet is pre-acknowledged only after the data packet is transmitted downstream to the recipient.
4. The method of claim 1, wherein controlling the flow of data packets received from the sender comprises sending a packet to the sender, wherein the packet includes a TCP window having a size that is set to allow the sender to transmit a desired number of packets.
5. The method of claim 4, wherein the size of the TCP window is set to zero to disallow additional data packets from the sender.
6. The method of claim 1, wherein controlling the flow of data packets received from the sender comprises skipping a predetermined fraction of the acknowledgements sent to the sender.
7. The method of claim 1, wherein the data packets are sent over the network using the TCPIP protocol.
8. A method for pre-acknowledging data packets sent over a network connection, the method comprising:
intercepting a data packet from a sender to a recipient;
transmitting the data packet to the recipient;
retaining a copy of the transmitted data packet;
sending an acknowledgement to the sender for the data packet;
determining whether the data packet has been delivered to the recipient or has been lost;
retransmitting the data packet if the data packet has been determined lost;
discarding the data packet if the data packet has been determined delivered; and
controlling the flow of additional packets sent by the sender.
9. The method of claim 8, wherein the acknowledgement for the data packet is sent to the sender only after the data packet is transmitted to the recipient.
10. The method of claim 8, wherein controlling the flow of additional packets comprises sending a packet to the sender, wherein the packet includes a TCP window having a size that is set to allow the sender to transmit a desired number of packets.
11. The method of claim 10, wherein the size of the TCP window is set to zero to disallow additional data packets from the sender.
12. The method of claim 8, wherein controlling the flow of additional packets comprises using a TCP delayed ACK mechanism.
13. The method of claim 8, wherein the data packet is sent over the network connection using the TCPIP protocol.
14. The method of claim 8, wherein the data packet is intercepted before a high-loss link in the network connection.
15. The method of claim 8, wherein the data packet is intercepted at a point in the network connection having a bandwidth mismatch, with a lower bandwidth downstream of the point of interception.
16. The method of claim 8, wherein the data packet is intercepted at a point in the network having a latency transition.
17. In a flow control module communicatively coupled via a network between a sender and a recipient, a method of terminating the sender’s connection with the recipient, the method comprising:
a step for pre-acknowledging packets received by the flow control module from the sender so that the sender operates as if the pre-acknowledged packets have been received by the recipient;
a step for handling retransmission to the recipient of any lost packets as needed; and
a step for controlling the flow of packets transmitted by the sender.
18. A computer program product for handling retransmission and acknowledgements of data packets transmitted from a sender to a recipient over a network, the computer program product comprising a computer-readable medium containing computer program code for performing the operations:
receiving data packets from the sender;
transmitting the received data packets downstream to the recipient;
pre-acknowledging the received data packets by sending acknowledgments to the sender before receiving acknowledgements from a downstream entity for the data packets; and
controlling the flow of data packets received from the sender.
19. The computer program product of claim 18, the computer program code further for performing the operation:
retaining a copy of the transmitted data packets until acknowledged as received from a downstream entity.
20. The computer program product of claim 18, wherein each data packet is pre-acknowledged only after the data packet is transmitted downstream to the recipient.
21. The computer program product of claim 18, wherein controlling the flow of data packets received from the sender comprises sending a packet to the sender, wherein the packet includes a TCP window having a size that is set to allow the sender to transmit a desired number of packets.
22. The computer program product of claim 21, wherein the size of the TCP window is set to zero to disallow additional data packets from the sender.
23. The computer program product of claim 18, wherein controlling the flow of data packets received from the sender comprises skipping a predetermined fraction of the acknowledgements sent to the sender.
24. The computer program product of claim 18, wherein the data packets are sent over the network using the TCPIP protocol.
25. A computer program product for pre-acknowledging data packets sent over a network connection, the computer program product comprising a computer-readable medium containing computer program code for performing the operations:
intercepting a data packet from a sender to a recipient;
transmitting the data packet to the recipient;
retaining a copy of the transmitted data packet;
sending an acknowledgement to the sender for the data packet;
determining whether the data packet has been delivered to the recipient or has been lost;
retransmitting the data packet if the data packet has been determined lost;
discarding the data packet if the data packet has been determined delivered; and
controlling the flow of additional packets sent by the sender.
26. The computer program product of claim 25, wherein the acknowledgement for the data packet is sent to the sender only after the data packet is transmitted to the recipient.
27. The computer program product of claim 25, wherein controlling the flow of additional packets comprises sending a packet to the sender, wherein the packet includes a TCP window having a size that is set to allow the sender to transmit a desired number of packets.
28. The computer program product of claim 27, wherein the size of the TCP window is set to zero to disallow additional data packets from the sender.
29. The computer program product of claim 25, wherein controlling the flow of additional packets comprises using a TCP delayed ACK mechanism.
30. The computer program product of claim 25, wherein the data packet is sent over the network connection using the TCPIP protocol.
31. The computer program product of claim 25, wherein the data packet is intercepted before a high-loss link in the network connection.
32. The computer program product of claim 25, wherein the data packet is intercepted at a point in the network connection having a bandwidth mismatch, with a lower bandwidth downstream of the point of interception.
33. The computer program product of claim 25, wherein the data packet is intercepted at a point in the network having a latency transition.
34. A flow control module for handling retransmission and acknowledgements of data packets transmitted from a sender to a recipient over a network, the flow control module comprising:
a network interface for receiving data packets from the sender and transmitting data packets to the recipient;
a preack module configured to send an early acknowledgement to the sender for data packets received therefrom before receiving an acknowledgement from a downstream entity for the data packets; and
a memory coupled to the network interface, the memory configured to store data packets until acknowledged as received by a downstream entity;
an overflow control module for controlling the flow of packets received from the sender.
35. The flow control module of claim 34, wherein the network interface retransmits lost data packets.
36. The flow control module of claim 35, wherein the preack module sends an early acknowledgement for each data packet only after the network interface transmits the data packet to the recipient.
37. The flow control module of claim 34, wherein the overflow control module controls the flow by sending a packet to the sender, wherein the packet includes a TCP window having a size that is set to allow the sender to transmit a desired number of packets.
38. The flow control module of claim 37, wherein the size of the TCP window is set to zero to disallow additional data packets from the sender.
39. The flow control module of claim 34, wherein the overflow control module controls the flow by skipping a predetermined fraction of the acknowledgements sent to the sender.
40. The flow control module of claim 34, wherein the data packets are sent over the network using the TCPIP protocol.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A clock processing circuit wherein input clocks are converted into stabilized output clocks, comprising:
(a) a first level shifter and a second level shifter;
(b) first and second buffer circuits for producing stabilized output clocks;
(c) a first output conductive path from the first level shifter and a second output conductive path from the second level shifter provided to the first buffer and a second buffer over the first and second conductive paths respectively; and
(d) the first buffer being disposed adjacent to the first level shifter and the second buffer being disposed adjacent to the second level shifter so that the delay amount of clocks on two conductive paths is reduced and a difference in delay amounts between these clocks is reduced or suppressed.
2. A clock processing circuit for stabilizing a pair of input clocks having complementary phases and outputting a pair of stabilized clocks, the clock processing circuit coupled to a power source voltage, comprising:
a first converting circuit for converting the pair of input clocks into a pair of clocks having an amplitude in accordance with the power source voltage and outputting a first converted clock having a first phase, the first converted clock being one of the pair of converted clocks;
a second converting circuit for converting the pair of input clocks into a pair of clocks having an amplitude in accordance with the power source voltage and outputting a second converted clock having a second phase opposite to the first phase, the second converted clock being one of the pair of converted clocks;
a first buffer circuit disposed adjacent to the first converting circuit and responsive to the first converted clock for outputting a first stabilized clock which is stabilized by buffering the first converted clock; and
a second buffer circuit disposed adjacent to the second converting circuit and responsive to the second converted clock for outputting a second stabilized clock which is stabilized by buffering the second converted clock;
a first connecting path for conducting the first converted clock to the first buffer circuit and a second connecting path for conducting the second converted clock to the second buffer circuit with the length of the first and second conducting paths being selected to be substantially the same;
whereby first and second stabilized clocks having complementary phases are produced.
3. A clock processing circuit according to claim 2, wherein:
each of the first buffer circuit and the second buffer circuit is formed by a plurality of inverter circuits connected in parallel to each other, each inverter including a p-channel transistor and an n-channel transistor which are connected in series between a positive power source and a negative power source and each inverter receiving an input signal at control terminals of the transistors and obtaining an output signal whose phase has been inverted at a connecting terminal of the transistors.
4. A clock processing circuit according to claim 2 wherein:
each of the first converting circuit, the second converting circuit, the first buffer circuit, and the second buffer circuit is formed using a thin film transistor as an active element.
5. A clock processing circuit according to claim 2 wherein:
each of the first converting circuit and the second converting circuit level-shifts an input clock and outputs a level-shifted clock.
6. A clock processing circuit according to claim 2 wherein:
the first converting circuit and the second converting circuit have the same structure.
7. A clock processing circuit according to claim 2 wherein:
the first converting circuit and the second converting circuit have common input paths for a pair of input clocks.