1. A textured wire tie comprising a frictional textured coating adhered to a surface of a metal wire having a tensile strength of between about 30,000 to about 75,000 pounds per square inch, wherein the coating comprises a melt blend of a first plastic resin having a first melt index between about 14 to about 19 and a second plastic resin having a second melt index between about 0.3 to about 0.9 such that, upon the melt blend being applied to the metal wire, and solidified, the difference between the first plastic resin’s melt index and the second plastic resin’s melt index causes formation of a roughened outer surface of the textured coating that reduces slippage of the textured wire tie on itself when twisted, or slippage during handling.
2. The textured wire tie of claim 1, wherein the first and second resins are polyvinyl chloride.
3. The textured wire tie of claim 1, wherein the first resin is a high density fractional melt polyvinyl chloride and the second resin is a 0.3 fractional melt polyvinyl chloride.
4. The textured wire tie of claim 3, wherein the first resin is from about 50% to about 70% by weight of the coating and the second resin is from 30% to about 50% by weight of the coating.
5. The textured wire tie of claim 3, wherein the first resin is about 60% by weight of the coating and the second resin is about 40% by weight of the coating.
6. The textured wire tie of claim 1, wherein the coating is from between about 0.005 to about 0.05 inches thick.
7. The textured wire tie of claim 1, wherein the wire is from 0.04 to about 0.80 inches in diameter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resistance variable memory element comprising:
a first electrode;
a first chalcogenide glass layer electrically coupled to said first electrode;
a first metal layer over said first chalcogenide glass layer;
a metal containing layer over said metal layer;
a second chalcogenide glass layer over said metal containing layer;
a second metal layer over and in contact with said second chalcogenide glass layer;
a conductive adhesion layer over and in contact with said second metal layer; and
a second electrode electrically coupled to said conductive adhesion layer.
2. The resistance variable memory element of claim 1, wherein said metal containing layer is a silver-chalcogenide layer.
3. The resistance variable memory element of claim 2, wherein said metal containing layer is silver-selenide.
4. The resistance variable memory element of claim 1, wherein said metal containing layer has a thickness of about 1 to 5 times the thickness of the first and second chalcogenide glass layers.
5. The resistance variable memory element of claim 1, wherein said metal containing layer has a thickness of about 470.
6. The resistance variable memory element of claim 1, wherein said first metal layer and said second metal layer are silver.
7. The resistance variable memory element of claim 6, wherein said first silver layer has a thickness of about 35 to about 50.
8. The resistance variable memory element of claim 6, wherein said second silver layer has a thickness of about 200.
9. The resistance variable memory element of claim 6, wherein said first chalcogenide glass layer and said second chalcogenide glass layer each have a thickness of about 100 to about 1000.
10. The resistance variable memory element of claim 1, wherein said first chalcogenide glass layer comprises silver-doped chalcogenide glass.
11. The resistance variable memory element of claim 1, wherein said first chalcogenide glass layer and said second chalcogenide glass layer each have a thickness of about 150.
12. The resistance variable memory element of claim 1, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise a material having a formula GexSe100\u2212x, where x=17 to 43.
13. The resistance variable memory element of claim 1, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise germanium selenide glass having a stoichiometry of about Ge40Se60.
14. The resistance variable memory element of claim 1, wherein said conductive adhesion layer is a chalcogenide glass layer.
15. The resistance variable memory element of claim 14, wherein said conductive adhesion layer is germanium selenide glass having a stoichiometry of about Ge40Se60.
16. The resistance variable memory element of claim 14, wherein said conductive adhesion layer has a thickness of about 100.
17. The resistance variable memory element of claim 1, wherein said first and second electrodes are selected from the group consisting of tungsten, nickel, tantalum, aluminum, platinum, and conductive nitrides.
18. The resistance variable memory element of claim 17, wherein said first electrode is tungsten.
19. The resistance variable memory element of claim 17, wherein said second electrode is tantalum nitride.
20. A method of forming a resistance variable memory element comprising:
forming a first electrode;
forming a first chalcogenide glass layer;
forming a first metal layer electrically coupled to said first chalcogenide glass layer;
forming a metal containing layer over said metal layer;
forming a second chalcogenide glass layer over said metal containing layer;
forming a second metal layer over and in contact with said second chalcogenide glass layer;
forming a conductive adhesion layer over and in contact with said second metal layer; and
forming a second electrode electrically coupled to said conductive adhesion layer.
21. The method of claim 20, wherein said metal containing layer is a silver-chalcogenide layer.
22. The method of claim 21, wherein said metal containing layer is silver-selenide.
23. The method of claim 20, wherein said metal containing layer has a thickness of about 1 to 5 times the thickness of the first and second chalcogenide glass layers.
24. The method of claim 20, wherein said metal containing layer has a thickness of about 470.
25. The method of claim 20, wherein said first and second metal layers are silver.
26. The method of claim 25, wherein said first silver layer has a thickness of about 35 to about 50.
27. The method of claim 25, wherein said second silver layer has a thickness of about 200.
28. The method of claim 20, wherein said first chalcogenide glass layer and said second chalcogenide glass layer each have a thickness of about 100 to about 1000.
29. The method of claim 28, wherein said first chalcogenide glass layer and said second chalcogenide glass layer each have a thickness of about 150.
30. The method of claim 20, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise a material having a formula GexSe100\u2212x, where x=17 to 43.
31. The method of claim 20, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise germanium selenide glass having a stoichiometry of about Ge40Se60.
32. The method of claim 20, wherein said conductive adhesion layer is a chalcogenide glass layer.
33. The resistance variable memory element of claim 32, wherein said conductive adhesion layer is germanium selenide glass having a stoichiometry of about Ge40Se60.
34. The method of claim 33, wherein said conductive adhesion layer has a thickness of about 100.
35. The method of claim 33, further comprising the step of applying a conditioning potential across the memory element structure.
36. The method of claim 34, wherein the pulse width of said conditioning potential ranges from about 100 nanoseconds to about 500 nanoseconds.
37. A resistance variable memory element comprising:
a first electrode;
a first chalcogenide glass layer electrically coupled to said first electrode;
a second chalcogenide glass layer over said first chalcogenide glass layer;
a metal containing layer between said first and second chalcogenide glass layers, said metal containing layer having a different composition than said first and second chalcogenide glass layers;
a first metal layer between said first chalcogenide glass layer and said metal containing layer;
a second metal layer over and in contact with said second chalcogenide glass layer;
a third chalcogenide glass layer over and in contact with said second metal layer; and
a second electrode electrically coupled to said third chalcogenide glass layer.
38. The resistance variable memory element of claim 27, wherein said metal containing layer is a silver-chalcogenide layer.
39. The resistance variable memory element of claim 38, wherein said metal containing layer is silver-selenide.
40. The resistance variable memory element of claim 37, wherein said metal containing layer has a thickness of about 1 to 5 times the thickness of the first and second chalcogenide glass layers.
41. The resistance variable memory element of claim 37, wherein said metal containing layer has a thickness of about 470.
42. The resistance variable memory element of claim 37, wherein at least one of said first and second metal layers is silver.
43. The resistance variable memory element of claim 37, wherein said first chalcogenide glass layer and said second chalcogenide glass layer each have a thickness of about 100 to about 1000.
44. The resistance variable memory element of claim 37, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise a material having a formula GexSe100\u2212x, where x=17 to 43.
45. The resistance variable memory element of claim 37, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise germanium selenide glass having a stoichiometry of about Ge40Se60.
46. The resistance variable memory element of claim 37, wherein said first and second electrodes are selected from the group consisting of tungsten, nickel, tantalum, aluminum, platinum, silver, and conductive nitrides.
47. The resistance variable memory element of claim 37, wherein said first chalcogenide glass layer comprises silver-doped chalcogenide glass.
48. A method of forming a resistance variable memory element comprising the steps of:
forming a first electrode;
forming a first chalcogenide glass layer electrically coupled to said first electrode;
forming a second chalcogenide glass layer over said first chalcogenide glass layer;
forming a metal containing layer between said first and second chalcogenide glass layers;
forming a first metal layer between said first chalcogenide glass layer and said metal containing layer;
forming a second metal layer over and in contact with said second chalcogenide glass layer;
forming a third chalcogenide glass layer over and in contact with said second metal layer; and
forming a top electrode electrically coupled to said third chalcogenide glass layer.
49. The method of claim 48, wherein said metal containing layer is a silver-chalcogenide layer.
50. The method of claim 48, wherein said metal containing layer is silver-selenide.
51. The method of claim 48, wherein said metal containing layer has a thickness of about 1 to 5 times the thickness of the first and second chalcogenide glass layers.
52. The method of claim 48, wherein said metal containing layer has a thickness of about 470.
53. The method of claim 48, wherein at least one of said first and second metal layers is silver.
54. The method of claim 48, wherein said first chalcogenide glass layer and said second chalcogenide glass layer each have a thickness of about 100 to about 1000.
55. The method of claim 48, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise a material having a formula GexSe100\u2212x, where x =17 to 43.
56. The method of claim 55, wherein said first chalcogenide glass layer and said second chalcogenide glass layer comprise germanium selenide glass having a stoichiometry of about Ge40Se60.
57. The method of claim 48, further comprising the step of applying a conditioning potential across the memory element structure.
58. The method of claim 57, wherein the pulse width of said conditioning potential ranges from about 100 nanoseconds to about 500 nanoseconds.