1. A vehicle control apparatus comprising:
an actuator controlling a drive of a vehicle;
a main calculator calculating an instructed drive power based on a requested drive power of the vehicle and instructing the actuator to operate according to the instructed drive power; and
a monitor section monitoring at least one of (i) the instructed drive power or (ii) an actual drive power that is output from the actuator according to the instructed drive power, wherein
based on a drive power excess amount calculated by deducting the requested drive power from either the actual drive power or the instructed drive power,
the vehicle control apparatus performs an in-excess determination control that executes a fail-safe action regarding a drive of the vehicle by (i) monitoring a drive power in-excess indicator started at a time of a temporary in-excess state of the drive power excess amount in which the drive power excess amount exceeds a predetermined value, and (ii) determining that the drive power is in excess when the drive power in-excess indicator exceeds a preset indicator threshold, and
when performing the in-excess determination control, the vehicle control apparatus lowers the indicator threshold when a vehicle-dynamic safety parameter that reflects a travel safety related vehicle behavior fulfills a prescribed condition.
2. The vehicle control apparatus of claim 1, wherein
the drive power in-excess indicator is at least one of
(i) an excess drive power continuation time during which a drive power in-excess state continues after a start of when the drive power excess amount temporarily exceeds the predetermined value,
(ii) an absolute value of the drive power excess amount, or
(iii) a time integration value of the drive power excess amount.
3. The vehicle control apparatus of claim 1, wherein
the vehicle-dynamic safety parameter is at least one of an amount of depression of a brake pedal, an amount of depression of an accelerator pedal, a steer angle of a steering wheel, a steering speed of the steering wheel, a steering angle of a front tire or a rear tire, a vehicle speed, an acceleration of the vehicle, a yaw angular velocity, a yaw angular acceleration, a difference between wheel speeds, a road surface friction coefficient, or a shift position.
4. The vehicle control apparatus of claim 1, wherein
a lowering amount of the indicator threshold of the driver power in-excess indicator is changed according to a value of the vehicle-dynamic safety parameter.
5. The vehicle control apparatus of claim 4, wherein
the vehicle-dynamic safety parameter represents a high degree of dangerous vehicle behavior when the value of the vehicle-dynamic safety parameter is large,
the indicator threshold is lowered when the value of the vehicle-dynamic safety parameter is equal to or greater than a specified value, and
the lowering amount of the indicator threshold is increased in proportion to an increase of the value of the vehicle-dynamic safety parameter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A slew rate control circuit comprising:
a first circuit, said first circuit outputting a signal with a controllable rising time in response to a first digital code; and
a second circuit, said second circuit outputting the signal with a controllable falling time in response to a second digital code.
2. The control circuit of claim 1, wherein said first circuit is a digitally controlled resistive network.
3. The control circuit of claim 2, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor being activated by one bit of the first digital code.
4. The control circuit of claim 3, wherein said digitally controlled resistive network comprises four parallel connected transistors.
5. The control circuit of claim 2, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor having a same size or a different size and being activated by one bit of the first digital code.
6. The control circuit of claim 5, wherein said digitally controlled resistive network comprises four parallel connected PMOS transistors, each PMOS transistor having a different size and being activated by one bit of the first digital code.
7. The control circuit of claim 1, wherein said second circuit is a digitally controlled resistive network.
8. The control circuit of claim 7, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor being activated by one bit of the second digital code.
9. The control circuit of claim 8, wherein said digitally controlled resistive network comprises four parallel connected transistors.
10. The control circuit of claim 7, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor having a same size or a different size and being activated by one bit of the second digital code.
11. The control circuit of claim 10, wherein said digitally controlled resistive network comprises four parallel connected NMOS transistors, each NMOS transistor having a different size and being activated by one bit of the second digital code.
12. The control circuit of claim 1, further comprising a third circuit connected between said first and second circuits, said third circuit enabling one of said first and second circuits at a time.
13. A slew rate control circuit comprising:
means for outputting a boosted signal with a variable rising time in response to a first digital code; and
means for outputting the boosted signal with a variable falling time in response to a second digital code.
14. An imaging device comprising:
an array of pixels organized into a plurality of rows and columns; and
a row driver circuit connected to the rows of pixels, said row driver circuit comprising a plurality of slew rate control circuits, each slew rate control circuit comprising:
a first circuit, said first circuit outputting a signal with a controllable rising time in response to a first digital code, and
a second circuit, said second circuit outputting the signal with a controllable falling time in response to a second digital code.
15. The device claim 14, wherein said first circuit is a digitally controlled resistive network.
16. The device of claim 15, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor being activated by one bit of the first digital code.
17. The device of claim 16, wherein said digitally controlled resistive network comprises four parallel connected transistors.
18. The device of claim 15, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor having a same size or a different size and being activated by one bit of the first digital code.
19. The device of claim 18, wherein said digitally controlled resistive network comprises four parallel connected PMOS transistors, each PMOS transistor having a different size and being activated by one bit of the first digital code.
20. The device of claim 14, wherein said second circuit is a digitally controlled resistive network.
21. The device of claim 20, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor being activated by one bit of the second digital code.
22. The device of claim 21, wherein said digitally controlled resistive network comprises four parallel connected transistors.
23. The device of claim 20, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor having a same size or a different size and being activated by one bit of the second digital code.
24. The device of claim 23, wherein said digitally controlled resistive network comprises four parallel connected NMOS transistors, each NMOS transistor having a different size and being activated by one bit of the second digital code.
25. The device of claim 14, further comprising a third circuit connected between said first and second circuits, said third circuit enabling one of said first and second circuits at a time.
26. The device of claim 14, wherein at least some of the slew rate control circuits generate a reset control circuit for the pixels.
27. The device of claim 26, wherein other slew rate control circuits generate a transfer control circuit for the pixels.
28. The device of claim 14, wherein two slew rate control circuits are associated with and connected to a respective row of pixels.
29. The device of claim 14, wherein the signal is a boosted transistor gate control signal.
30. The device of claim 14, wherein the signal is a boosted supply voltage signal.
31. An imaging device comprising:
an array of pixels organized into a plurality of rows and columns; and
a row driver circuit connected to the rows of pixels, said row driver circuit comprising a plurality of slew rate control circuits, each slew rate control circuit comprising:
means for outputting a boosted signal with a variable rising time in response to a first digital code, and
means for outputting the boosted signal with a variable falling time in response to a second digital code.
32. A system comprising:
a processor; and
an imager, said imager comprising an array of pixels organized into a plurality of rows and columns and a row driver circuit connected to the rows of pixels, said row driver circuit comprising a plurality of slew rate control circuits, each slew rate control circuit comprising:
a first circuit, said first circuit outputting a signal with a controllable rising time in response to a first digital code, and
a second circuit, said second circuit outputting the signal with a controllable falling time in response to a second digital code.
33. The system of claim 32, wherein said first circuit is a digitally controlled resistive network.
34. The system of claim 33, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor being activated by one bit of the first digital code.
35. The system of claim 34, wherein said digitally controlled resistive network comprises four parallel connected transistors.
36. The system of claim 33, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor having a same size or a different size and being activated by one bit of the first digital code.
37. The system of claim 36, wherein said digitally controlled resistive network comprises four parallel connected PMOS transistors, each PMOS transistor having a different size and being activated by one bit of the first digital code.
38. The system of claim 32, wherein said second circuit is a digitally controlled resistive network.
39. The system of claim 38, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor being activated by one bit of the second digital code.
40. The system of claim 39, wherein said digitally controlled resistive network comprises four parallel connected transistors.
41. The system of claim 40, wherein said digitally controlled resistive network comprises a plurality of parallel connected transistors, each transistor having a same size or a different size and being activated by one bit of the second digital code.
42. The system of claim 41, wherein said digitally controlled resistive network comprises four parallel connected NMOS transistors, each NMOS transistor having a different size and being activated by one bit of the second digital code.
43. The system of claim 32, further comprising a third circuit connected between said first and second circuits, said third circuit enabling one of said first and second circuits at a time.
44. The system of claim 32, wherein at least some of the slew rate control circuits generate a reset control circuit for the pixels.
45. The system of claim 44, wherein other slew rate control circuits generate a transfer control circuit for the pixels.
46. The system of claim 32, wherein two slew rate control circuits are associated with and connected to a respective row of pixels.
47. The system of claim 32, wherein the signal is a boosted transistor gate control signal.
48. The system of claim 32, wherein the signal is a boosted supply voltage signal.
49. A method of operating an imager, said method comprising the acts of:
generating a first digital code;
altering a resistance of a first resistive network based on the first digital code; and
applying a first voltage to the altered first resistive network to generate a boosted signal having a controllable rising rate.
50. The method of claim 49 further comprising:
generating a second digital code;
altering a resistance of a second resistive network based on the second digital code; and
applying a second voltage to the altered second resistive network to generate the boosted signal with a controllable falling rate.
51. The method of claim 49, wherein the boosted signal is a reset control signal.
52. The method of claim 49, wherein the boosted signal is a transfer control signal.
53. The method of claim 49, wherein the boosted signal is a supply voltage signal.
54. A method of manufacturing a slew rate control circuit, said method comprising the acts of:
providing a first circuit, said first circuit having a first input for receiving a first digital code and a first output for outputting a signal with a rising time corresponding to the first digital code;
providing a second circuit, said second circuit having a second input for receiving a second digital code and a second output for outputting the signal with a falling time corresponding to the second digital code; and
connecting the first and second outputs to form an output node whereby the signal is output.
55. The method of claim 54, wherein said act of providing the first circuit comprises providing a digitally controlled resistive network.
56. The method of claim 54, wherein said act of providing the first circuit comprises providing a plurality of parallel connected transistors, wherein each transistor is connected to one bit of the first digital code.
57. The method of claim 54, wherein said act of providing the first circuit comprises providing a plurality of parallel connected transistors, wherein each transistor has a same size or a different size and is connected to one bit of the first digital code.
58. The method of claim 54, wherein said act of providing the second circuit comprises providing a digitally controlled resistive network.
59. The method of claim 54, wherein said act of providing the second circuit comprises providing a plurality of parallel connected transistors, wherein each transistor is connected to one bit of the second digital code.
60. The method of claim 54, wherein said act of providing the second circuit comprises providing a plurality of parallel connected transistors, wherein each transistor has a different size and is connected to one bit of the second digital code.