1-9. (canceled)
10. The submerged gas processor of claim 30, further including a reinforcing plate attached to the vessel and attached to the weir.
11. The submerged gas processor of claim 10, further including a stabilizer ring attached to the reinforcing plate and disposed between the gas tube and the weir.
12-15. (canceled)
16. The submerged gas processor of claim 30, further including a jacket disposed adjacent to an outer wall of the vessel that may be used for either heating or cooling the process liquid.
17. The submerged gas processor of claim 16, wherein the jacket includes a fluid volume that enables heating or cooling fluid to circulate adjacent the vessel.
18. The submerged gas processor of claim 16, wherein the jacket includes an electrical heating element.
19-29. (canceled)
30. A submerged gas processor comprising:
a vessel capable of holding a fluid, wherein the fluid, when disposed in an at rest condition within the vessel defines an at rest fluid level within the vessel;
a fluid inlet disposed within the vessel;
a gas tube extending into the vessel adapted to transport a gas into the interior of the vessel, the gas tube including a gas exit port disposed below the at rest fluid level;
an exhaust port disposed in the vessel adapted to transport gas from the interior of the vessel; and
a weir, having a first end and a second end, the weir disposed adjacent the gas exit port within the vessel to create a confined volume between the tube and the weir; wherein the weir includes a first end and a second end and wherein at least a substantial portion of the weir is disposed below the at rest fluid level within the vessel so as to form a first circulation gap between the first weir end and a first wall of the vessel and to form a second circulation gap between the second weir end and a second wall of the vessel.
31. (canceled)
32. The submerged gas processor of claim 30, wherein the second end of the weir is disposed at or above the at rest fluid level of the vessel.
33. (canceled)
34. The submerged gas processor of claim 30, further including a baffle disposed within the vessel at or above the at rest fluid level of the vessel.
35. The submerged gas processor of claim 30, further including a baffle disposed within the vessel above the second end of the weir.
36. (canceled)
37. (canceled)
38. The submerged gas processor of claim 30, further including a heating device associated with the vessel.
39. The submerged gas processor of claim 30, further including a cooling device associated with the vessel.
40. The submerged gas processor of claim 30, wherein the weir comprises a tubular member disposed around the gas tube.
41. The submerged gas processor of claim 40, wherein the tubular member is circular in cross section.
42. The submerged gas processor of claim 40, wherein the tubular member is disposed co-axial to the gas tube.
43-59. (canceled)
60. A submerged gas processor comprising:
a vessel;
a fluid inlet disposed within the vessel;
a weir disposed within the vessel to define a first volume and a second volume within the vessel;
a gas delivery tube extending into the vessel, the gas delivery tube including a gas exit disposed in the first volume;
a gas exhaust port disposed in the vessel; and
a biogas burner attached to the gas delivery tube;
wherein the weir includes a first weir end and a second weir end and is disposed within the vessel to create a first fluid circulation path adjacent the first weir end to allow fluid to flow from the first volume to the second volume and to create a second fluid circulation path adjacent the second weir end to allow fluid to flow from the second volume to the first volume when gas is introduced into the first volume from the gas exit.
61. The submerged gas processor of claim 60, the first weir end is disposed above the gas exit and the second weir end is disposed below the gas exit.
62. The submerged gas processor of claim 60, wherein the first volume is smaller than the second volume.
63. The submerged gas processor of claim 60, wherein the second fluid circulation path is formed between the second weir end and a bottom wall of the vessel.
64. The submerged gas processor of claim 60, further including a baffle disposed within the vessel above the first volume adjacent the first weir end.
65. The submerged gas processor of claim 60, further including a heating device disposed adjacent an outer wall of the vessel or associated with the vessel.
66. The submerged gas processor of claim 60, further including a cooling device disposed within or adjacent to the vessel.
67-69. (canceled)
70. The submerged gas processor of claim 60, wherein the weir comprises a generally flat plate member.
71. The submerged gas processor of claim 70, wherein the generally flat plate member extends across the vessel between opposite sides of the vessel.
72. The submerged gas processor of claim 60, further including a burner that operates on gaseous or liquid fuel attached to the gas tube.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit adapted to receive data bits of a packet via a N-bit bus and generate a cyclic redundancy check for the packet, the integrated circuit comprising:
a first dividing logic comprising M dividers each adapted to receive and divide a different one of the NM bits of the data by a first generator polynomial, wherein the divider receiving the first of the NM bits of data supplies a first output signal;
a second dividing logic adapted to receive the first output signal, said second dividing logic comprising P dividers each adapted to receive and divide a different one of the NP bits of the data it receives by the first generator polynomial to generate a remainder, said second dividing logic further adapted to supply one of the NP remainders as a second output signal; and
a third dividing logic adapted to receive and divide the second output signal by a second generator polynomial.
2. The integrated circuit of claim 1 wherein each of the NM bits of the data received by the first dividing logic belongs to a new packet and wherein each of the NP bits of the data received by the second dividing logic belongs to a current packet.
3. The integrated circuit of claim 1 wherein said second dividing logic further comprise a multiplexer adapted to receive each of the NP remainders at its input terminals and supply the second output signal at its output terminal.
4. The integrated circuit of claim 1 wherein said first generator polynomial is of 123rd degree.
5. The integrated circuit of claim 4 wherein said 123rd generator polynomial is defined by:
x123+x111+x92+x84+x64+x46+x231.
6. The integrated circuit of claim 1 wherein said second generator polynomial is of 32nd degree.
7. The integrated circuit of claim 6 wherein said second generator polynomial is defined by:
\u2003x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1.
8. The integrated circuit of claim 1 wherein N is 128.
9. The integrated circuit of claim 8 wherein each of M and P is 8.
10. A method for generating a cyclic redundancy check for a packet whose data are carried over a N-bit bus, the method comprising:
dividing each NM bits of the data by a first generator polynomial;
dividing each NP bits of the data by the first generator polynomial to generate NP remainders;
selecting one of the NP remainders as an output signal; and
dividing the output signal by a second generator polynomial.
11. The method of claim 10 wherein each of the NM bits of the data belongs to a new packet and wherein each of the NP bits of the data belongs to a current packet.
12. The method of claim 10 wherein said first generator polynomial is of 123rd degree.
13. The method of claim 12 wherein said 123rd generator polynomial is defined by:
x123+x111+x92+x84+x64+x46+x23+1.
14. The method of claim 10 wherein said second generator polynomial is of 32nd degree.
15. The method of claim 14 wherein said second generator polynomial is defined by:
g(x)=x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1.
16. The method of claim 10 wherein N is 128.
17. The method of claim 16 wherein each of M and P is 8.
18. An integrated circuit adapted to receive data bytes of a packet via a 16-byte wide bus and generate a 32-bit cyclic redundancy check for the packet, each byte including 8 bits, the integrated circuit comprising:
a decoder adapted to receive a control signal and generate 15 pointer signals each associated with a different one of the 15 most significant bytes of the data;
a first dividing logic comprising:
sixteen dividers each adapted to receive a different one of the sixteen bytes of the data and divide the received data by a first generator polynomial of 123rd degree; wherein the divider receiving the 16th byte of data receives a start signal and wherein the divider receiving the 1st byte of the data supplies a first output signal; and
fifteen multiplexers each receiving the start signal at its first input terminal and each receiving at its select terminal a different one of the 15 pointer signals, wherein the multiplexer receiving the pointer signal associated with the ith byte of the data receives the remainder of the division performed on (i+1)th byte of the data at its second input terminal and supplies a signal to the divider adapted to divided the ith byte of the data;
a second dividing logic comprising:
sixteen dividers each adapted to receive a different one of the sixteen bytes of the data and divide the received data by the first generator polynomial to generate a remainder; wherein the divider adapted to divide the ith byte of the data receives the remainder of the division performed on the (i+1)th byte of the data; and
a multiplexer receiving the remainder generated by each of the sixteen dividers in the second dividing logic at its input terminals and receiving the control signal at its select terminal, wherein said multiplexer supplies a second output signal;
a second multiplexer adapted to supply one of the first and second output signals to that divider in the second dividing logic which is adapted to divide (i+1)th byte of the data; said second multiplexer adapted to receive at it select terminal a signal that is a delayed replica of a start-of-packet signal; and
a third dividing logic adapted to receive and divide the second output signal by a second generator polynomial of 32nd degree.
19. The integrated circuit of claim 18 wherein said first generator polynomial is:
x123+x111+x92+x84+x64+x46+x23+1.
20. The integrated circuit of claim 18 wherein said second generator polynomial is:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1.
21. The integrated circuit of claim 18 wherein the signal received by the select terminal of the second multiplexer is generated one clock cycle after the start-of-packet signal arrives.
22. The integrated circuit of claim 18, wherein said decoder is further adapted to receive an abort signal, an end-of-packet signal and the start-of-packet signal.
23. The integrated circuit of claim 18 wherein if the decoder receives the start-of-packet signal, data bytes belonging to a current packet are divided by the second dividing logic and the data bytes belonging to a new packet are divided by the first dividing logic.
24. The integrated circuit of claim 18 further comprising:
a register adapted to receive and supply the 16 bytes of the data to the first and second diving logic.
25. The integrated circuit of claim 24 wherein said third dividing logic is further adapted to receive an end-of-packet signal and a 32-bit initial value.