1. An integrated circuit having an auto-calibration circuit to minimize input offset voltage in an operational amplifier, comprising:
an operational amplifier having differential inputs, an output and a digitally controlled input offset voltage compensation circuit; and
an auto-calibration circuit comprising
a voltage comparator having first and second inputs,
a voltage reference coupled to the first input of the voltage comparator,
a voltage offset trim digital-to-analog converter (DAC),
voltage offset calibration switches,
a successive approximation register (SAR) having an input coupled to an output of the voltage comparator and outputs coupled to the voltage offset trim DAC, and
calibration logic;
wherein when an event occurs the calibration logic controls the voltage offset calibration switches to couple the differential inputs of the operational amplifier to the voltage reference and the output of the operational amplifier to the second input of the voltage comparator;
whereby the voltage comparator causes the SAR to change output values to the voltage offset trim DAC so as to minimize an input offset voltage of the operational amplifier during an auto-calibration cycle initiated by the event.
2. The integrated circuit of claim 1, wherein the event is a user auto-calibration request.
3. The integrated circuit of claim 1, wherein the event is a power-on-reset.
4. The integrated circuit of claim 1, wherein the event is detection of a parity error in a stored auto-calibration data value.
5. The integrated circuit of claim 1, wherein the event is an ending time of an auto-calibration timer.
6. The integrated circuit of claim 5, wherein the auto-calibration timer time is programmable.
7. The integrated circuit of claim 1, wherein the event is a change in temperature of the integrated circuit.
8. The integrated circuit of claim 1, wherein the event is a change in supply voltage.
9. The integrated circuit of claim 1, further comprising an offset compensation latch register connected between the SAR and the voltage offset trim DAC, wherein the offset compensation latch register stores the SAR output value used to minimize the input offset voltage of the operational amplifier.
10. The integrated circuit of claim 1, wherein the voltage reference is programmable.
11. The integrated circuit of claim 1, further comprising the operational amplifier having a calibration output.
12. The integrated circuit of claim 11, wherein the calibration output instead of the output of the operational amplifier is coupled to the second input of the voltage comparator with the voltage offset calibration switches.
13. The integrated circuit of claim 12, wherein the output of the operational amplifier is a tri-state output and is decoupled from the calibration output when the input offset voltage of the operational amplifier is being minimized.
14. The integrated circuit of claim 1, wherein said auto-calibration circuit causes said operational amplifier to have high gain during the auto-calibration cycle.
15. The integrated circuit of claim 1, further comprising switches for selecting each one of a plurality of operational amplifiers during respective auto-calibration cycles therefore.
16. The integrated circuit of claim 15, further comprising:
a plurality of voltage offset trim DACs; and
a plurality of offset compensation latch registers connected between the SAR and respective ones of the plurality of voltage offset trim DACs, wherein each one of the plurality of offset compensation latch registers stores the SAR output value used to minimize the input offset voltage of respective ones of the plurality of operational amplifiers.
17. A method for minimizing an input offset voltage in an analog input device upon an occurrence of an event, said method comprising the steps of:
(a) detecting an occurrence of an event;
(b) switching from a normal mode to an auto-calibration mode upon detection of the occurrence of the event an analog input device having an input offset voltage compensation circuit;
(c) applying a reference voltage to the analog input device;
(d) minimizing an input offset voltage of the analog input device by:
(i) measuring an output voltage of the analog input device; and
(ii) applying input offset compensation values to the input offset voltage compensation circuit until the output voltage from the analog input device is at a desired value and then storing the input offset compensation value that minimizes the input offset voltage of the analog input device; and
(e) switching the analog input device from the calibration mode to the normal mode.
18. The method of claim 17, wherein the event is a user auto-calibration request.
19. The method of claim 17, wherein the event is a power-on-reset.
20. The method of claim 17, wherein the event is detection of a parity error in a stored auto-calibration data value.
21. The method of claim 17, wherein the event is an ending time of an auto-calibration timer.
22. The method of claim 17, wherein the step of switching the analog input device to a calibration mode includes the step of configuring the analog input device for high gain.
23. The method of claim 17, wherein the step of applying a reference voltage further comprises the step of applying a programmable reference voltage.
24. The method of claim 17, wherein the analog input device is a plurality of analog input devices and steps (b)-(e) are repeated for each one of the plurality of analog input devices.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Device for controlling disconnection of the cylinders in internal combustion engines, comprising at least one control device acting on a switchable element for valve actuation of valves and permitting in one of two switching states an actuation of the valve concerned, including transmission devices which, in dependence on a switch over state of the control device, transmit a cam rise produced by a camshaft to the valve provided with the switchable element, and a control unit acting on the control device, wherein the device has a data memory for detection of a time course of movement behavior of the gas exchange valves of the cylinders of the internal combustion engine, and a data processing unit which provides a combination of gas exchange valves into valve groups with regard to a common activation or deactivation, and passes on to the control unit in which an activation or deactivation instant is allocated to the valve groups, and which drives the control device by which the switchable elements for valve actuation of the valves belonging to the valve group are actuated.
2. Device according to claim 1, wherein, for determination of a parameter for selection and allocation of the valves to the valve group, a selection program for coincidence testing control times (20) of the gas exchange valves is present in the data processing unit (22), and therewith a size of a switch over window (18, 19) for simultaneous actuation of selected valves is concluded from a degree of coincidence.
3. Device according to claim 2, wherein a determination of a minimum number of control devices (16, 17) takes place in the selection program of the data processing unit (22) in dependence on a breadth of the changeover window (18, 19).
4. Device according to claim 1, wherein for a grouping of the valves into a valve group, only those are permitted by the data processing unit (22) which at an instant of driving the switchable elements (7) have the valve actuators in a closed state or at a sufficiently great distance from a beginning of a next cam rise.
5. Device according to claim 1, wherein a hydraulically driven system is provided as the control device (16, 17).
6. Device according to claim 1, wherein the control device includes two control valves (16, 17).
7. Device according to claim 1, wherein at least one intake valve and at least one exhaust valve, which belong to different combustion chambers, are actuated by action of the control device (16, 17) on the switchable elements (7) allocated to the valves.