1460897332-f49e8a5c-d72e-4f88-a412-5fd0a4945c60

1. A high-throughput system for rapidly determining the proliferative status of primitive hematopoietic cells by luminescence output comprising:
a. a target cell population of mononuclear cells comprising primitive hematopoietic cells;
b. a medium comprising serum and methyl cellulose;
c. a proliferation agent specific for a single subpopulation of primitive hematopoietic cells, the proliferation agent comprising one or more growth factors, one or more cytokines, or combinations thereof;
d. a reagent capable of reacting with ATP and generating luminescence in the presence of ATP; and
e. a plate;
wherein the target cell population, the medium, the proliferation agent, and the reagent capable of reacting with ATP are combined in an order to determine the proliferative status of the subpopulation of primitive hematopoietic cells by detecting the level of luminescence generated from the reagent that reacted with the ATP, and
wherein the level of luminescence detected indicates the amount of ATP in the subpopulation of primitive hematopoietic cells, and the amount of ATP in the subpopulation of primitive hematopoietic cells indicates the proliferative status of the subpopulation of primitive hematopoietic cells.
2. The system of claim 1, wherein the proliferation agent is further selected from the group consisting of erythropoietin, granulocyte-macrophage colony stimulating factor, granulocyte colony stimulating factor, macrophage colony stimulating factor, thrombopoietin, stem cell factor, interleukin-1, interleukin-2, interleukin-3, interleukin-6, interleukin-7, interleukin-15, Flt3L, leukemia inhibitory factor, and combinations thereof.
3. The system of claim 2, further comprising instructions for determining the proliferative status of the subpopulation of primitive hematopoietic cells by luminescence output.
4. The system of claim 3, wherein the target cell population of mononuclear cells further comprises a population of human or animal hematopoietic cells.
5. The system of claim 3, further comprising an ATP standard solution.
6. The system of claim 4, wherein the serum further comprises bovine serum albumin, an insulin, an iron-saturated transferrin, and Iscove’s modified Dulbecco’s medium (IMDM).
7. The system of claim 6, wherein the insulin is recombinant insulin.
8. The system of claim 1 further comprising:
a. the medium having a concentration of fetal bovine serum between 0% to about 30% by volume;
b. the methyl cellulose having a concentration of between about 0.4% to about 0.7%, by weight;
c. an atmosphere having a concentration of oxygen between about 3.5% oxygen and about 7.5% oxygen by volume; and
d. instructions for determining the luminescence generated by the reagent capable of reacting with ATP and generating luminescence in the presence of ATP.
9. The system of claim 1, wherein the proliferation agent is selected from the group consisting of erythropoietin, granulocyte-macrophage colony stimulating factor, granulocyte colony stimulating factor, macrophage colony stimulating factor, thrombopoietin, stem cell factor, interleukin-1, interleukin-2, interleukin-3, interleukin-6, interleukin-7, interleukin-15, Flt3L, leukemia inhibitory factor, and combinations thereof.
10. The system of claim 8, wherein the concentration of fetal bovine serum in the medium is between 0% and about 10% by volume.
11. The system of claim 8, wherein the concentration of methyl cellulose in the medium is about 0.7% by weight.
12. The system of claim 8, wherein the concentration of oxygen in the atmosphere is about 5% by volume.
13. The system of claim 8, wherein the target cell population further comprises an enriched population of hematopoietic stem cells.
14. The system of claim 8, wherein the target cell population further comprises a population enriched in at least one hematopoietic progenitor cell lineage.
15. The system of claim 8, wherein the target cell population further comprises hematopoietic stem cells.
16. The system of claim 8, wherein the target cell population further comprises hematopoietic progenitor cells.
17. The system of claim 8, wherein the target cell population further comprises hematopoietic stem cells and hematopoietic progenitor cells.
18. The system of claim 8, wherein the target cell population further comprises primary hematopoietic cells.
19. The system of claim 18, wherein the primary hematopoietic cells are isolated from an animal tissue selected from the group consisting of peripheral blood, bone marrow, umbilical cord blood, yolk sac, fetal liver, and spleen.
20. The system of claim 19, wherein the animal tissue is obtained from a human.
21. The system of claim 19, wherein the animal tissue is obtained from a mammal.
22. The system of claim 21, wherein the mammal is selected from the group consisting of cow, sheep, pig, horse, goat, dog, cat, non-human primates, rodents, rabbit, and hare.
23. The system of claim 18, wherein the primary hematopoietic cells are isolated from peripheral blood.
24. The system of claim 8, wherein the target cell population further comprises a differentially distinguishable subpopulation of primitive hematopoietic cells, wherein the differentially distinguishable subpopulation of primitive hematopoietic cells is defined by a cell surface marker thereon.
25. The system of claim 24, further comprising:
a. a cell surface marker indicator capable of selectively binding to a cell surface marker on the differentially distinguishable subpopulation of primitive hematopoietic cells; and
b. instructions for selectively isolating the differentially distinguishable subpopulation of primitive hematopoietic cells binding the indicator.
26. The system of claim 24, wherein the cell surface marker is CD34.
27. The system of claim 24, wherein the cell surface marker is selected from the group consisting of CD3, CD4, CD8, CD34, CD90 (Thy-1) antigen, CD117, CD38, CD56, CD61, CD41, glycophorin A, HLA-DR, and CD133.
28. The system of claim 25, wherein a magnetic bead separation system is used to selectively isolate the differentially distinguishable subpopulation of primitive hematopoietic cells.
29. The system of claim 25, wherein a flow cytometry and cell sorting apparatus is used to selectively isolate the differentially distinguishable subpopulation of primitive hematopoietic cells.
30. The system of claim 8, wherein the single subpopulation of primitive hematopoietic cells comprises a stem cell lineage selected from the group consisting of colony-forming cell-blast (CFC-blast), high proliferative potential colony forming cell (HPP-CFC), and colony-forming unit-granulocyte, erythroid, macrophage, megakaryocyte (CFU-GEMM).
31. The system of claim 8, wherein the single subpopulation of primitive hematopoietic cells comprises a hematopoietic progenitor cell lineage selected from the group consisting of granulocyte-macrophage colony-forming cell (GM-CFC), megakaryocyte colony-forming cell (Mk-CFC), macrophage colony-forming cell (M-CFC), granulocyte colony forming cell (G-CFC), burst-forming unit erythroid (BFU-E), colony-forming unit-erythroid (CFU-E), colony-forming cell-basophil (CFC-Bas), colony-forming cell-eosinophil (CFC-Eo), B cell colony-forming cell (B-CFC), and T cell colony-forming cell (T-CFC).
32. The system of claim 8, wherein the reagent capable of generating luminescence in the presence of ATP comprises luciferin and luciferase.
33. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of stem cell factor, interleukin-6, Flt3L, and combinations thereof.
34. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of macrophage colony stimulating factor, interleukin-1, interleukin-3, interleukin-6, stem cell factor, and combinations thereof.
35. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of erythropoietin, granulocyte-macrophage colony stimulating factor, granulocyte colony stimulating factor, stem cell factor, interleukin-3, interleukin-6, Flt3L, and combinations thereof.
36. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of (a) erythropoietin, (b) erythropoietin and interleukin-3, (c) erythropoietin and stem cell factor, and (d) erythropoietin, stem cell factor, and interleukin-3.
37. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of (a) granulocyte-macrophage colony stimulating factor, (b) granulocyte-macrophage colony stimulating factor and interleukin-3, and (c) granulocyte-macrophage colony stimulating factor, interleukin-3, and stem cell factor.
38. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of (a) thrombopoietin, and (b) thrombopoietin, interleukin-3, and interleukin-6.
39. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of (a) interleukin-2, and (b) interleukin-7, Flt3L, and interleukin-15.
40. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of (a) interleukin-7, and (b) interleukin-7 and Flt3L.
41. The system of claim 8, wherein the proliferation agent is erythropoietin.
42. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of granulocyte colony stimulating factor and granulocyte-macrophage colony stimulating factor.
43. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of (a) interleukin-3, and (b) interleukin-3 and stem cell factor.
44. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of granulocyte-macrophage colony stimulating factor, interleukin-3, interleukin-5, and combinations thereof.
45. The system of claim 8, wherein the proliferation agent is further selected from the group consisting of (a) macrophage colony stimulating factor, (b) macrophage colony stimulating factor and granulocyte-macrophage colony stimulating factor, and (c) granulocyte-macrophage colony stimulating factor.
46. The system of claim 8, further comprising:
a. a test compound capable of contacting the target cell population; and
b. instructions to determine the ability of the test compound to modulate the proliferation of the target cell population.
47. The system of claim 46, further comprising instructions to determine the ability of the test compound to modulate the differentiation of the target cell population.
48. The system of claim 8, wherein the system further comprises:
a. the target cell population comprising a plurality of target cell subpopulations;
b. at least one test compound capable of contacting the plurality of target cell subpopulations;
c. instructions to determine the ability of the at least one test compound to alter the proliferation of the target cell population by comparing the proliferative status of the plurality of target cell subpopulations with the proliferative status of a target population of cells not in contact with the at least one test compound; and
d. instructions to identify the at least one test compound modulating the proliferative status of the target cell population.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A display device comprising an active matrix panel,
the display device further comprising:
a first scan signal line driving circuit; and
a second scan signal line driving circuit,
wherein of all scan signal lines consisting of (i) a first group of scan signal lines connected to the first scan signal line driving circuit and (ii) a second group of scan signal lines connected to the second scan signal line driving circuit, the scan signal lines in the first group and the scan signal lines in the second group are disposed in an alternate manner,
the first scan signal line driving circuit including a first shift register which receives two clock signals that are first and second clock signals,
the first shift register having stages each of which includes first and second clock input terminals,
the first shift register being arranged to have first stages and second stages alternately cascaded with each other, each of the first stages being such that the first clock signal is supplied to the first clock input terminal, and the second clock signal is supplied to the second clock input terminal, each of the second stages being such that the second clock signal is supplied to the first clock input terminal, and the first clock signal is supplied to the second clock input terminal,
the stages of the first shift register, upon receipt of a shift pulse from a preceding stage, each outputting a scan pulse by transferring a clock pulse of a clock signal supplied through the first clock input terminal to a scan signal line corresponding to the individual stage,
the stages of the first shift register each including a first transistor that is provided so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, the first transistor having a gate receiving a clock signal supplied through the second clock input terminal,
the second scan signal line driving circuit including a second shift register which receives two clock signals that are third and fourth clock signals,
the second shift register having stages each of which includes third and fourth clock input terminals,
the second shift register being arranged to have third stages and fourth stages alternately cascaded with each other, each of the third stages being such that the third clock signal is supplied to the third clock input terminal, and the fourth clock signal is supplied to the fourth clock input terminal, each of the fourth stages being such that the fourth clock signal is supplied to the third clock input terminal, and the third clock signal is supplied to the fourth clock input terminal,
the stages of the second shift register, upon receipt of a shift pulse from a preceding stage, each outputting a scan pulse by transferring a clock pulse of a clock signal supplied through the third clock input terminal to a scan signal line corresponding to the individual stage,
the stages of the second shift register each including a second transistor that is provided so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, the second transistor having a gate receiving a clock signal supplied through the fourth clock input terminal,
wherein timings for the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are such that a clock pulse of the first clock signal appears subsequently to a clock pulse of the fourth clock signal, a clock pulse of the third clock signal appears subsequently to a clock pulse of the first clock signal, a clock pulse of the second clock signal appears subsequently to the clock pulse of the third clock signal, and the clock pulse of the fourth clock signal appears subsequently to the clock pulse of the second clock signal.
2. A display device comprising an active matrix panel,
the display device further comprising:
a first scan signal line driving circuit; and
a second scan signal line driving circuit,
wherein of all scan signal lines consisting of (i) a first group of scan signal lines connected to the first scan signal line driving circuit and (ii) a second group of scan signal lines connected to the second scan signal line driving circuit, the scan signal lines in the first group and the scan signal lines in the second group are disposed in an alternate manner,
the first scan signal line driving circuit including a first shift register which receives four clock signals that are first, second, and third, fourth clock signals,
the first shift register having stages each of which includes first, second, third, and fourth clock input terminals,
the first shift register being arranged to have first stages and second stages alternately cascaded with each other, each of the first stages being such that the first clock signal is supplied to the first clock input terminal, the second clock signal is supplied to the second clock input terminal, the third clock signal is supplied to the third clock input terminal, and the fourth clock signal is supplied to the fourth clock input terminal, each of the second stages being such that the second clock signal is supplied to the first clock input terminal, the first clock signal is supplied to the second clock input terminal, the fourth clock signal is supplied to the third clock input terminal, and the third clock signal is supplied to the fourth clock input terminal,
the stages of the first shift register, upon receipt of a shift pulse from a preceding stage, each outputting a scan pulse by transferring a clock pulse, of a clock signal supplied through the first clock input terminal to a scan signal line corresponding to the individual stage,
the stages of the first shift register each including: a first transistor that is provided so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, the first transistor having a gate receiving a clock signal supplied through the second clock input terminal; a second transistor that is provided so as to connect and disconnect the scan signal line corresponding to the individual stage to and from the low-level power source, the second transistor having a gate to which a clock pulse of a clock signal supplied through the third clock input terminal is applied; and a third transistor that is provided so as to connect and disconnect the scan signal line corresponding to the individual stage to and from the low-level power source, the third transistor having a gate to which a clock pulse of a clock signal supplied through the fourth clock input terminal is applied,
the second scan signal line driving circuit including a second shift register which receives the four clock signals that are the first, second, and third, fourth clock signals,
the second shift register having stages each of which includes fifth, sixth, seventh, and eighth clock input terminals,
the second shift register being arranged to have third stages and fourth stages alternately cascaded with each other, each of the third stages being such that the third clock signal is supplied to the fifth clock input terminal, the fourth clock signal is supplied to the sixth clock input terminal, the first clock signal is supplied to the seventh clock input terminal, and the second clock signal is supplied to the eighth clock input terminal, each of the fourth stages being such that the fourth clock signal is supplied to the fifth clock input terminal, the third clock signal is supplied to the sixth clock input terminal, the second clock signal is supplied to the seventh clock input terminal, and the first clock signal is supplied to the eighth clock input terminal,
the stages of the second shift register, upon receipt of a shift pulse from a preceding stage, each outputting a scan pulse by transferring a clock pulse of a clock signal supplied through the fifth clock input terminal to a scan signal line corresponding to the individual stage,
the stages of the second shift register each including: a fourth transistor that is provided so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, the fourth transistor having a gate receiving a clock signal supplied through the sixth clock input terminal; a fifth transistor that is provided so as to connect and disconnect the scan signal line corresponding to the individual stage to and from the low-level power source, the fifth transistor having a gate to which a clock pulse of a clock signal supplied through the seventh clock input terminal is applied; and a sixth transistor that is provided so as to connect and disconnect the scan signal line corresponding to the individual stage to and from the low-level power source, the sixth transistor having a gate to which a clock pulse of a clock signal supplied through the eighth clock input terminal is applied,
wherein timings for the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are such that a clock pulse of the first clock signal appears subsequently to a clock pulse of the fourth clock signal, a clock pulse of the third clock signal appears subsequently to a clock pulse of the first clock signal, a clock pulse of the second clock signal appears subsequently to the clock pulse of the third clock signal, and the clock pulse of the fourth clock signal appears subsequently to the clock pulse of the second clock signal.
3. The display device according to claim 1, wherein
one of the first and second scan signal line drive circuits is provided in one of two regions adjoining a display region of the panel in a direction in which the scan signal lines extend, and
the other scan signal line drive circuit is provided in the other region adjoining the display region of the panel.
4. A display device comprising an active matrix panel,
the display device further comprising a scan signal line driving circuit that is provided in a region adjoining a display region of the panel in a direction in which scan signal lines extend and that includes first and second shift registers connected to the scan signal lines,
wherein of all of the scan signal lines consisting of (i) a first group of scan signal lines connected to the first shift register and (ii) a second group of scan signal lines connected to the second shift register, the scan signal lines in the first group and the scan signal lines in the second group are disposed in an alternate manner,
the first shift register receiving two clock signals that are first and second clock signals,
the first shift register having stages each of which includes first and second clock input terminals,
the first shift register being arranged to have first stages and second stages alternately cascaded with each other, each of the first stages being such that the first clock signal is supplied to the first clock input terminal, and the second clock signal is supplied to the second clock input terminal, each of the second stages being such that the second clock signal is supplied to the first clock input terminal, and the first clock signal is supplied to the second clock input terminal,
the stages of the first shift register, upon receipt of a shift pulse from a preceding stage, each outputting a scan pulse by transferring a clock pulse of a clock signal supplied through the first clock input terminal to a scan signal line corresponding to the individual stage,
the stages of the first shift register each including a first transistor that is provided so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, the first transistor having a gate receiving a clock signal supplied through the second clock input terminal,

the second shift register receiving two clock signals that are third and fourth clock signals,
the second shift register having stages each of which includes third and fourth clock input terminals,
the second shift register being arranged to have third stages and fourth stages alternately cascaded with each other, each of the third stages being such that the third clock signal is supplied to the third clock input terminal and that the fourth clock signal is supplied to the fourth clock input terminal, each of the fourth stages being such that the fourth clock signal is supplied to the third clock input terminal and that the third clock signal is supplied to the fourth clock input terminal,
the stages of the second shift register, upon receipt of a shift pulse from a preceding stage, each outputting a scan pulse by transferring a clock pulse of a clock signal supplied through the third clock input terminal to a scan signal line corresponding to the individual stage,
the stages of the second shift register each including a second transistor that is provided so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, the second transistor having a gate receiving a clock signal supplied through the fourth clock input terminal,
wherein timings for the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are such that a clock pulse of the first clock signal appears subsequently to a clock pulse of the fourth clock signal, a clock pulse of the third clock signal appears subsequently to a clock pulse of the first clock signal, a clock pulse of the second clock signal appears subsequently to the clock pulse of the third clock signal, and the clock pulse of the fourth clock signal appears subsequently to the clock pulse of the second clock signal.
5. The display device according to claim 1, wherein
the first and second scan signal line drive circuits are monolithically formed in the panel.
6. The display device according to claim 4, wherein
the scan signal line drive circuit is monolithically formed in the panel.
7. The display device according to claim 5, wherein
the panel is formed from amorphous silicon.
8. The display device according to claim 5, wherein
the panel is formed from polycrystalline silicon.
9. The display device according to claim 5, wherein
the panel is formed from CG silicon.
10. The display device according to claim 5, wherein
the panel is formed from microcrystalline silicon.
11. A method for driving a display device comprising an active matrix panel,
the display device further comprising:
a first scan signal line driving circuit including a first shift register; and
a second scan signal line driving circuit including a second shift register,
wherein of all scan signal lines consisting of (i) a first group of scan signal lines connected to the first scan signal line driving circuit and (ii) a second group of scan signal lines connected to the second scan signal line driving circuit, the scan signal lines in the first group and the scan signal lines in the second group are disposed in an alternate manner,
the method comprising:
supplying two clock signals that are first and second clock signals to each of stages of the first shift register;
causing the stages of the first shift register to operate so that first stages and second stages are alternately arranged, each of the first stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the first clock signal to a scan signal line corresponding to the individual stage, each of the second stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the second clock signal to a scan signal line corresponding to the individual stage;
causing each of the first stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the second clock signal is supplied to a gate of a transistor provided in each of the first stages;
causing each of the second stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the first clock signal is supplied to a gate of a transistor provided in each of the second stages;

supplying two clock signals that are third and fourth clock signals to each of stages of the second shift register;
causing the stages of the second shift register to operate so that third stages and fourth stages are alternately arranged, each of the third stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the third clock signal to a scan signal line corresponding to the individual stage, each of the fourth stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the fourth clock signal to a scan signal line corresponding to the individual stage;
causing each of the third stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the fourth clock signal is supplied to a gate of a transistor provided in each of the third stages; and
causing each of the fourth stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the third clock signal is supplied to a gate of a transistor provided in each of the fourth stages,
wherein timings for the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are such that the clock pulse of the first clock signal appears subsequently to the clock pulse of the fourth clock signal, the clock pulse of the third clock signal appears subsequently to the clock pulse of the first clock signal, the clock pulse of the second clock signal appears subsequently to the clock pulse of the third clock signal, and the clock pulse of the fourth clock signal appears subsequently to the clock pulse of the second clock signal.
12. A method for driving a display device comprising an active matrix panel,
the display device further comprising:
a first scan signal line driving circuit including a first shift register; and
a second scan signal line driving circuit including a second shift register,
wherein of all scan signal lines consisting of (i) a first group of scan signal lines connected to the first scan signal line driving circuit and (ii) a second group of scan signal lines connected to the second scan signal line driving circuit, the scan signal lines in the first group and the scan signal lines in the second group are disposed in an alternate manner,
the method comprising:
supplying four clock signals that are first, second, third, and fourth clock signals to each of stages of the first shift register;
causing the stages of the first shift register to operate so that first stages and second stages are alternately arranged, each of the first stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the first clock signal to a scan signal line corresponding to the individual stage, each of the second stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the second clock signal to a scan signal line corresponding to the individual stage;
causing each of the first stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the second, third, or fourth clock signal is supplied to each gate of three transistors provided in each of the first stages;
causing each of the second stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the first, third, or fourth clock signal is supplied to each gate of three transistors provided in each of the second stages;
supplying four clock signals that are the first, second, third, and fourth clock signals to each of stages of the second shift register;
causing the stages of the second shift register to operate so that third stages and fourth stages are alternately arranged, each of the third stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the third clock signal to a scan signal line corresponding to the individual stage, each of the fourth stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the fourth clock signal to a scan signal line corresponding to the individual stage;
causing each of the third stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the first, second, or fourth clock signal is supplied to each gate of three transistors provided in each of the third stages; and
causing each of the fourth stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the first, second, or third clock signal is supplied to each gate of three transistors provided in each of the fourth stages,
wherein timings for the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are such that the clock pulse of the first clock signal appears subsequently to the clock pulse of the fourth clock signal, the clock pulse of the third clock signal appears subsequently to the clock pulse of the first clock signal, the clock pulse of the second clock signal appears subsequently to the clock pulse of the third clock signal, and the clock pulse of the fourth clock signal appears subsequently to the clock pulse of the second clock signal.
13. The display device according to claim 11, wherein
one of the first and second scan signal line drive circuits is provided in one of two regions adjoining a display region of the panel in a direction in which the scan signal lines extend, and
the other scan signal line drive circuit is provided in the other region adjoining the display region of the panel.
14. A method for driving a display device comprising an active matrix panel,
the display device further comprising a scan signal line driving circuit that is provided in a region adjoining a display region of the panel in a direction in which scan signal lines extend and that includes first and second shift registers connected to the scan signal lines,
wherein of all of the scan signal lines consisting of (i) a first group of scan signal lines connected to the first shift register and (ii) a second group of scan signal lines connected to the second shift register, the scan signal lines in the first group and the scan signal lines in the second group are disposed in an alternate manner,
the method comprising:
supplying two clock signals that are first and second clock signals to each of stages of the first shift register;
causing the stages of the first shift register to operate so that first stages and second stages are alternately arranged, each of the first stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the first clock signal to a scan signal line corresponding to the individual stage, each of the second stages operating to, upon receipt of a shift pulse from a preceding stage, output a scan pulse by transferring a clock pulse of the second clock signal to a scan signal line corresponding to the individual stage;
causing each of the first stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the second clock signal is supplied to a gate of a transistor provided in each of the first stages;
causing each of the second stages to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, when the first clock signal is supplied to a gate of a transistor provided in each of the second stages;