1. A 4-way power splittercombiner circuit for use with power amplifiers, comprising:
a splitter circuit, further comprising
an input port;
a first node;
a second node;
a first splitter transmission line having an impedance ZS1 and an electrical length \u03a6S1, said first splitter transmission line for connecting said input port to said first node;
a second splitter transmission line having an impedance ZS2 and an electrical length \u03a6S2, said second splitter transmission line for connecting said input port to said second node;
a first amplifier input;
a second amplifier input;
a third amplifier input;
a fourth amplifier input;
a third splitter transmission line having an impedance ZS3 and an electrical length \u03a6S3, said third splitter transmission line for connecting said first node to said first amplifier input;
a fourth splitter transmission line having an impedance ZS4 and an electrical length \u03a6S4, said fourth splitter transmission line for connecting said first node to said second amplifier input;
a fifth splitter transmission line having an impedance ZS5 and an electrical length \u03a6S5, said fifth splitter transmission line for connecting said second node to said third amplifier input;
a sixth splitter transmission line having an impedance ZS6 and an electrical length \u03a6S6, said sixth splitter transmission line for connecting said second node to said fourth amplifier input;
a combiner circuit, further comprising
an output port;
a third node;
a fourth node;
a first combiner transmission line having an impedance ZC1 and an electrical length \u03a6C1, said first combiner transmission line for connecting said output port to said third node;
a second combiner transmission line having an impedance ZC2 and an electrical length \u03a6C2, said second combiner transmission line for connecting said output port to said fourth node;
a first amplifier output;
a second amplifier output;
a third amplifier output;
a fourth amplifier output;
a third combiner transmission line having an impedance ZC3 and an electrical length \u03a6C3, said third combiner transmission line for connecting said third node to said first amplifier output;
a fourth combiner transmission line having an impedance ZC4 and an electrical length \u03a6C4, said fourth combiner transmission line for connecting said third node to said second amplifier output;
a fifth combiner transmission line having an impedance ZC5 and an electrical length \u03a6C5, said fifth combiner transmission line for connecting said fourth node to said third amplifier output;
a sixth combiner transmission line having an impedance ZC6 and an electrical length \u03a6C6, said sixth combiner transmission line for connecting said fourth node to said fourth amplifier output;
wherein said first amplifier input and said first amplifier output together define a first amplifier port, said second amplifier input and said second amplifier output together define a second amplifier port, said third amplifier input and said third amplifier output together define a third amplifier port, and said fourth amplifier input and said fourth amplifier output together define a fourth amplifier port, each said amplifier port for receiving an amplifier;
wherein said first amplifier port, said second amplifier port, said third amplifier port and said fourth amplifier port collectively accept one to four amplifiers and the fraction of power provided to each of said amplifiers is 1N where N is the number of operative amplifiers; and
wherein the phase shift of each of said combiner transmission lines and each of said splitter transmission lines is selected to produce an in-phase signal at said output port.
2. The 4-way power splittercombiner circuit of claim 1 wherein the electrical lengths of said transmission lines satisfy the following equations:
\u03a6S1+\u03a6S3=\u03a6S1+\u03a6S4=X;
\u03a6S2+\u03a6S5=\u03a6S2+\u03a6S6=Y;
\u03a6C1+\u03a6C3=\u03a6C1+\u03a6C4=X\u2032;
\u03a6C2+\u03a6C5=\u03a6C2+\u03a6C6=Y\u2032;
|X\u2212Y|=|X\u2032\u2212Y\u2032|=90 degrees; and
(X\u2212Y)=(Y\u2032\u2212X\u2032).
3. The 4-way power splittercombiner circuit of claim 1, further comprising at least one amplifier.
4. The 4-way power splittercombiner circuit of claim 3 wherein the impedance presented by said input port and said output port are between approximately 35 \u03a9 and approximately 71 \u03a9.
5. The 4-way power splittercombiner circuit of claim 3 wherein said at least one amplifier comprises a first amplifier in said second amplifier port.
6. The 4-way power splittercombiner circuit of claim 3 wherein said at least one amplifier comprises a first amplifier in said first amplifier port.
7. The 4-way power splittercombiner circuit of claim 6 wherein said at least one amplifier further comprises a second amplifier in said second amplifier port.
8. The 4-way power splittercombiner circuit of claim 7 wherein said at least one amplifier further comprises a third amplifier in said fourth amplifier port.
9. The 4-way power splittercombiner circuit of claim 7 wherein said at least one amplifier further comprises a third amplifier in said third amplifier port.
10. The 4-way power splittercombiner circuit of claim 9 wherein said at least one amplifier further comprises a fourth amplifier in said fourth amplifier port.
11. A 4-way power splittercombiner circuit for use with power amplifiers, comprising:
an input port;
a first splitter transmission line connecting a first amplifier input to a first splitter node, said first splitter transmission line comprising a first splitter impedance transformer segment having impedance of 59.46 \u03a9 and electrical length of 90\xb0 and a first splitter phase matching segment having impedance of 50 \u03a9 and electrical length of 270\xb0;
a second splitter transmission line connecting a second amplifier input to said first splitter node, said second splitter transmission line comprising a second splitter impedance transformer segment and a second splitter phase matching segment, each of said second splitter impedance transformer segment and said second splitter phase matching segment having impedance and electrical length substantially identical to that of said first splitter impedance transformer and said splitter first phase matching segment;
a third splitter transmission line connecting a third amplifier input to a second splitter node, said third splitter transmission line having impedance of 50 \u03a9 and electrical length of 180\xb0;
a fourth splitter transmission line connecting a fourth amplifier input to said second splitter node, said fourth splitter transmission line having impedance and electrical length substantially identical to that of said third splitter transmission line;
a fifth splitter transmission line connecting said second splitter node to said input port, said fifth splitter transmission line comprising a third splitter impedance transformer segment having impedance of 38 \u03a9 and electrical length of 90\xb0, and a fourth splitter impedance transformer segment having impedance of 64 \u03a9 and electrical length of 90\xb0;
a sixth splitter transmission line connecting said first splitter node to said input port, said sixth splitter transmission line having impedance of 50 \u03a9 and electrical length of 90\xb0;
an output port;
a first combiner transmission line connecting a first amplifier output to a first combiner node, said first combiner transmission line comprising a first combiner impedance transformer segment having impedance of 59.46 \u03a9 and electrical length of 90\xb0 and a first combiner phase matching segment having impedance of 50 \u03a9 and electrical length of 90\xb0;
a second combiner transmission line connecting a second amplifier output to said first combiner node, said second combiner transmission line comprising a second combiner impedance transformer segment and a second combiner phase matching segment, each of said second combiner impedance transformer segment and said second combiner phase matching segment having impedance and electrical length substantially identical to that of said first combiner impedance transformer and said combiner first phase matching segment;
a third combiner transmission line connecting a third amplifier output to a second combiner node, said third combiner transmission line having impedance of 50 \u03a9 and electrical length of 180\xb0;
a fourth combiner transmission line connecting a fourth amplifier output to said second combiner node, said fourth combiner transmission line having impedance and electrical length substantially identical to that of said third combiner transmission line;
a fifth combiner transmission line connecting said second combiner node to said output port, said fifth combiner transmission line comprising a third combiner impedance transformer segment having impedance of 38 \u03a9 and electrical length of 90\xb0, and a fourth combiner impedance transformer segment having impedance of 64 \u03a9 and electrical length of 90\xb0;
a sixth combiner transmission line connecting said first combiner node to said output port, said sixth combiner transmission line having impedance of 50 \u03a9 and electrical length of 90\xb0;
wherein said first amplifier input and said first amplifier output together define a first amplifier port for receiving an amplifier, said second amplifier input and said second amplifier output together define a second amplifier port for receiving an amplifier, said third amplifier input and said third amplifier output together define a third amplifier port for receiving an amplifier, said fourth amplifier input and said fourth amplifier output together define a fourth amplifier port for receiving an amplifier; and
wherein 1\u20134 power amplifiers may be inserted in said amplifier ports to provide an amplified signal.
12. A 4-way power splittercombiner circuit for use with power amplifiers, comprising:
a splitter circuit, further comprising
an input port;
a first node;
a second node;
a first splitter transmission line for connecting said input port to said first node;
a second splitter transmission line for connecting said input port to said second node;
a first amplifier input;
a second amplifier input;
a third amplifier input;
a fourth amplifier input;
a third splitter transmission line for connecting said first node to said first amplifier input;
a fourth splitter transmission line for connecting said first node to said second amplifier input;
a fifth splitter transmission line for connecting said second node to said third amplifier input;
a sixth splitter transmission line for connecting said second node to said fourth amplifier input;
a combiner circuit, further comprising
an output port;
a third node;
a fourth node;
a first combiner transmission line for connecting said output port to said third node;
a second combiner transmission line for connecting said output port to said fourth node;
a first amplifier output;
a second amplifier output;
a third amplifier output;
a fourth amplifier output;
a third combiner transmission line for connecting said third node to said first amplifier output;
a fourth combiner transmission line for connecting said third node to said second amplifier output;
a fifth combiner transmission line for connecting said fourth node to said third amplifier output;
a sixth combiner transmission line for connecting said fourth node to said fourth amplifier output;
wherein said first amplifier input and said first amplifier output together define a first amplifier port, said second amplifier input and said second amplifier output together define a second amplifier port, said third amplifier input and said third amplifier output together define a third amplifier port, and said fourth amplifier input and said fourth amplifier output together define a fourth amplifier port, each said amplifier port for receiving an amplifier;
wherein said splittercombiner circuit accepts one to four amplifiers and the fraction of power provided to each of said amplifiers is 1N where N is the number of operative amplifiers; and
wherein said splitter transmission lines and said combiner transmission lines have a plurality of electrical lengths; and
wherein the electrical lengths of each of said combiner transmission lines and each of said splitter transmission lines are selected to produce an in-phase signal at said output port.
13. The 4-way power splittercombiner circuit of claim 12 further comprising an amplifier.
14. The 4-way power splittercombiner circuit of claim 13 wherein said amplifier is populated in said first amplifier port.
15. The 4-way power splittercombiner circuit of claim 13 wherein said amplifier is populated in said second amplifier port.
16. A 4-way power splittercombiner circuit for use with power amplifiers, comprising:
a splitter circuit, further comprising
an input port;
a splitter node;
a first amplifier input;
a second amplifier input;
a third amplifier input;
a fourth amplifier input;
a first splitter transmission line having an impedance and an electrical length, said first splitter transmission line for connecting said input port to said splitter node;
a second splitter transmission line having an impedance and an electrical length, said second splitter transmission line for connecting said splitter node to said first amplifier input;
a third splitter transmission line having an impedance and an electrical length, said third splitter transmission line for connecting said splitter node to said second amplifier input;
a fourth splitter transmission line having an impedance and an electrical length, said fourth splitter transmission line for connecting said input port to said third amplifier input;
a fifth splitter transmission line having an impedance and an electrical length, said fifth splitter transmission line for connecting said input port to said fourth amplifier input;
a combiner circuit, further comprising
an output port;
a combiner node;
a first amplifier output;
a second amplifier output;
a third amplifier output;
a fourth amplifier output;
a first combiner transmission line having an impedance and an electrical length, said first combiner transmission line for connecting said output port to said combiner node;
a second combiner transmission line having an impedance and an electrical length, said second combiner transmission line for connecting said combiner node to said first amplifier output;
a third combiner transmission line having an impedance and an electrical length, said third combiner transmission line for connecting said combiner node to said second amplifier output;
a fourth combiner transmission line having an impedance and an electrical length, said fourth combiner transmission line for connecting said output port to said third amplifier output;
a fifth combiner transmission line having an impedance and an electrical length, said fifth combiner transmission line for connecting said output port to said fourth amplifier output;
wherein said first amplifier input and said first amplifier output together define a first amplifier port, said second amplifier input and said second amplifier output together define a second amplifier port, said third amplifier input and said third amplifier output together define a third amplifier port, and said fourth amplifier input and said fourth amplifier output together define a fourth amplifier port, each said amplifier port for receiving an amplifier;
wherein said splittercombiner circuit accepts one to four amplifiers and the fraction of power provided to each of said amplifiers is 1N where N is the number of operative amplifiers; and
wherein the electrical length of each of said combiner transmission lines and each of said splitter transmission lines is selected to produce an in-phase signal at said output port.
17. The 4-way power splittercombiner circuit of claim 16 further comprising an amplifier.
18. The 4-way power splittercombiner circuit of claim 17 wherein said amplifier is populated in said first amplifier port.
19. A splittercombiner circuit comprising:
an N-way splitter circuit including a common input port coupled to N-amplifier input ports by way of at least one splitter impedance transformation network, the N-amplifier input ports being configured to accommodate at least one of N-RF amplifiers installed in the splittercombiner circuit in a predetermined sequence, the at least one splitter impedance transformation network being characterized by at least one predetermined electric length and configured to provide each of the installed N-RF amplifiers with an RF amplifier input signal having an amplifier input signal power that is substantially equal to the signal power of a common input port signal divided by N, whereby N is an integer value between one (1) and four (4) inclusively; and
an N-way combiner circuit including N-amplifier output ports coupled to a common output port by way of at least one combiner impedance transformation network, the N-amplifier output ports corresponding to the N-amplifier input ports and configured to accommodate the at least one N-RF amplifiers installed in the splittercombiner circuit in the predetermined sequence, the at least one combiner impedance transformation network being characterized by the at least one predetermined electric length and configured as a schematic mirror image of the at least one splitter impedance transformation network.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power converter device, comprising:
a first pin;
a second pin;
an error amplifier having an input and an output, wherein the input of the error amplifier is coupled to the first pin;
a switch that is coupled to the second pin and the output of the error amplifier, that is operable to de-couple the second pin from the output of the error amplifier during a first stage of operation, and that is operable to couple the second pin to the output of the error amplifier during a second stage of operation;
a comparison circuit that is coupled to the switch so as to compare an external current to a plurality of reference currents from a plurality of current sources during the second stage of operation, wherein the comparison circuit includes a current minor circuit that is coupled to each of the current sources; and
a decoder that is operable to select a parameter during the first stage of operation as a function of a determined reference signal, wherein the decode includes:
a plurality of flip-flops that are each coupled to at least one of the portions of the comparison circuit; and
combinational logic that is coupled to each of the flip-flops.
2. The power converter of claim 1, wherein the combinational logic further comprises a plurality of logic gate, wherein each logic gate is coupled to at least one flip-flop.
3. The power converter of claim 1, wherein the comparison circuit further comprises:
a first branch that is coupled to the switch, wherein the second branch includes a first transistor that is diode-connected; and
a second branch that is coupled to at least one of the flip-flops, wherein the second branch includes:
a second transistor having a control electrode that is coupled to the control electrode of the first transistor; and
a first current source of the plurality of current sources having a first reference current that is coupled to the second transistor; and
a third branch that is coupled to at least one of the flip-flops, wherein the third branch includes:
a third transistor having a control electrode that is coupled to the control electrode of the first transistor; and
a second current source of the plurality of current sources having a second reference current that is coupled to the third transistor, wherein the magnitude of the first reference current is different from the magnitude of the second reference current.
4. The power converter of claim 1, wherein the power converter further comprises:
an oscillator;
a comparator that is coupled to the output of the error amplifier and to the oscillator; and
a pulse width modulation (PWM) control that is coupled to the comparator.
5. The power converter of claim 1, wherein the power converter further comprises a latch that is coupled to the decoder.
6. An integrated circuit (IC) comprising:
a first pin;
a second pin;
an error amplifier having an input and an output, wherein the input of the error amplifier is coupled to the first pin;
a switch that is coupled between the second pin and the output of the error amplifier; and
a selector that is coupled to the switch and that is adapted to actuate the switch to program the IC based at least in part on an external current, wherein the selector includes:
a first comparison branch including:
a first transistor that is diode-connected; and
a second transistor that is coupled between first transistor and the switch;
a second comparison branch including:
a third transistor having a control electrode that is coupled to the control electrode of the first transistor; and
a first current source having a first reference current that is coupled to the third transistor; and
a third comparison branch including:
a fourth transistor having a control electrode that is coupled to the control electrode of the first transistor;
a second current source having a second reference current that is coupled to the fourth transistor, wherein the magnitude of the first reference current is different from the magnitude of the second reference current; and
a decoder that selects a parameter based at least in part on the comparison of the external current to the first and second reference currents so as to program the apparatus, wherein the decoder includes:
a first flip-flop that is coupled to the second comparison branch;
a second flip-flop that is coupled to the third comparison branch; and
combinational logic that is coupled to the first and second flip-flops.
7. The IC of claim 6, wherein the combinational logic further comprises:
a first NOR gate that is coupled to the first and second flip-flops;
an inverter that is coupled to the first flip-flop;
a second NOR gate that is coupled to the inverter and to the second flip-flop; and
an AND gate that is coupled to the first and second flip-flops.
8. The IC of claim 6, wherein the first and second flip-flops are D flips-flops.
9. The IC of claim 6, wherein the IC further comprises a latch that is coupled to the decoder.
10. An apparatus comprising:
an IC having a first pin, a second pin, a third pin, and a fourth pin, wherein the IC includes:
an error amplifier having an input and an output, wherein the input of the error amplifier is coupled to the first pin;
a switch that is coupled between the second pin and the output of the error amplifier; and
a selector that is coupled to the switch and that is adapted to actuate the switch to program the IC based at least in part on an external current, wherein the selector includes:
a first comparison branch including:
a first transistor that is diode-connected; and
a second transistor that is coupled between first transistor and the second pin;
a second comparison branch including:
a third transistor having a control electrode that is coupled to the control electrode of the first transistor; and
a first current source having a first reference current that is coupled to the third transistor; and
a third comparison branch including:
a fourth transistor having a control electrode that is coupled to the control electrode of the first transistor;
a second current source having a second reference current that is coupled to the fourth transistor, wherein the magnitude of the first reference current is different from the magnitude of the second reference current; and
a decoder that selects a parameter based at least in part on the comparison of the external current to the first and second reference currents so as to program the apparatus, wherein the decoder includes:
a first flip-flop that is coupled to the second comparison branch;
a second flip-flop that is coupled to the third comparison branch; and
combinational logic that is coupled to the first and second flip-flops;
a fifth transistor that is coupled to the third pin at its control electrode and that is coupled to a node at one of its passive electrodes;
a sixth transistor that is coupled to the fourth pin at its control electrode and that is coupled to the node at one of its passive electrodes;
an inductor that is coupled to the node;
a capacitor that is coupled between the inductor and ground; and
a resistor that is coupled between the second pin and ground.
11. The apparatus of claim 10, wherein the combinational logic further comprises:
a first NOR gate that is coupled to the first and second flip-flops;
an inverter that is coupled to the first flip-flop;
a second NOR gate that is coupled to the inverter and to the second flip-flop; and
an AND gate that is coupled to the first and second flip-flops.
12. The apparatus of claim 10, wherein the first and second flip-flops are D flips-flops.
13. The apparatus of claim 10, wherein the IC further comprises a latch that is coupled to the decoder.