1. A semiconductor device, comprising:
a semiconductor substrate having a first conductivity type, including
a first diffusion region having the first conductivity type,
a second diffusion region having the first conductivity type, and
a channel region between the first diffusion region and the second diffusion region;
a control gate over the channel region; and
at least one sub-gate over the first and second diffusion regions.
2. The device of claim 1, wherein the first conductivity type is n-type.
3. The device of claim 1, wherein the first diffusion region and the second diffusion region have higher doping concentrations than the semiconductor substrate.
4. The device of claim 1, further comprising an inversion region having a second conductivity type in one of the first and second diffusion regions, wherein the semiconductor substrate further includes a third diffusion region having the second conductivity type, and wherein the inversion region is connectable to the third diffusion region for receiving a voltage bias.
5. The device of claim 1, wherein the control gate comprises polysilicon, a metal, or a metal silicide, or a combination thereof.
6. The device of claim 1, further comprising:
a first insulating layer over the channel region;
a trapping layer on the first insulating layer; and
a second insulating layer on the trapping layer,
wherein the control gate is over the second insulating layer.
7. The device of claim 1, wherein the at least one sub-gate comprises polysilicon, a metal, or a metal silicide, or a combination thereof.
8. The device of claim 1, further comprising a layer of gate dielectric between the at least one sub-gate and the first and second diffusion regions.
9. The device of claim 1, wherein the at least one sub-gate comprises one sub-gate over the first diffusion region, the second diffusion region, and the control gate.
10. The device of claim 1, further comprising:
a first insulating layer on the channel region and the first and second diffusion regions;
a trapping layer on the first insulating layer; and
a second insulating layer on the trapping layer,
wherein the at least one sub-gate comprises a first sub-gate over the first diffusion region and a second sub-gate over the second diffusion region, and wherein the first sub-gate, the second sub-gate, and the control gate are all on the second insulating layer.
11. A memory device, comprising:
a semiconductor substrate having a first conductivity type;
a plurality of memory cells arranged in a plurality of rows each corresponding to one of a plurality of word lines and a plurality of columns each corresponding to one of a plurality of bit lines, each memory cell comprising:
a first diffusion region having the first conductivity type in the semiconductor substrate,
a second diffusion region having the first conductivity type in the semiconductor substrate,
a channel region as a portion of the semiconductor substrate between the first and second diffusion regions,
a control gate over the channel region, and
at least one sub-gate over the first and second diffusion regions,
wherein the control gate is connected to the corresponding one of the word lines; and
a plurality of third diffusion regions having a second conductivity type, wherein each bit line includes two of the third diffusion regions at the ends of the corresponding bit line.
12. The device of claim 11, wherein the first conductivity type is n-type, and the second conductivity type is p-type.
13. The device of claim 11, wherein the first diffusion region and the second diffusion region of each memory cell have higher doping concentrations than the semiconductor substrate.
14. The device of claim 11, wherein the control gates of the memory cells comprise polysilicon, a metal, or a metal silicide, or a combination thereof.
15. The device of claim 11, each memory cell further comprising:
a first insulating layer on the channel region;
a trapping layer on the first insulating layer; and
a second insulating layer on the trapping layer,
wherein the control gate is over the second insulating layer.
16. The device of claim 11, wherein the at least one sub-gate of the memory cells comprise polysilicon, a metal, or a metal silicide, or a combination thereof.
17. The device of claim 11, each memory cell further comprising a layer of gate dielectric between the at least one sub-gate and the first and second diffusion regions.
18. The device of claim 11, wherein the at least one sub-gate of each memory cell comprises one sub-gate over both the first and second diffusion regions.
19. The device of claim 11, wherein the sub-gates of each column of the memory cells are electrically connected to one another and each memory cell is capable of storing two bits of information.
20. The device of claim 11, wherein adjacent ones of the memory cells in each column share the at least one sub-gate thereof.
21. The device of claim 11, wherein adjacent ones of the memory cells on the same bit line share one of the first and second diffusion regions.
22. The device of claim 11, each memory cell further comprising:
a first insulating layer on the channel region and the first and second diffusion regions;
a trapping layer on the first insulating layer; and
a second insulating layer on the trapping layer,
wherein the at least one sub-gate comprises a first sub-gate over the first diffusion region and a second sub-gate over the second diffusion region, and wherein the first sub-gate, the second sub-gate, and the control gate are all on the second insulating layer.
23. The device of claim 11, wherein the at least one sub-gate of each memory cell comprises a first sub-gate over the corresponding first diffusion region and a second sub-gate over the corresponding second diffusion region, and wherein each memory cell is capable of storing four bits of information.
24. A method of operating a memory cell, wherein the memory cell is formed on an n\u2212 semiconductor substrate, wherein the memory cell includes a first n\u2212 diffusion region and a second n\u2212 diffusion region in the semiconductor substrate, a channel region in the semiconductor substrate between the first n\u2212 diffusion region and the second n\u2212 diffusion region, a control gate over the channel region, and at least one sub-gate over the first and second n\u2212 diffusion regions, wherein the first and second n\u2212 diffusion regions have higher doping concentrations than the n\u2212 semiconductor substrate, the method comprising:
at least one of resetting the memory cell, erasing the memory cell, programming the memory cell, and reading the memory cell.
25. The method of claim 24, wherein resetting and erasing the memory cell comprises:
applying a negative voltage to the control gate, and
grounding or applying a positive voltage-to the semiconductor substrate.
26. The method of claim 24, wherein the memory cell further includes a first inversion region in the first n\u2212 diffusion region and a second inversion region in the second n\u2212 diffusion region, a first bit region and a second bit region each for storing one bit of information, the first bit region corresponding to the first inversion region and the second bit region corresponding to the second inversion region, wherein programming the memory cell comprises programming the first bit region or the second bit region,
wherein programming the first bit region includes
applying a positive voltage to the control gate,
applying a first negative voltage to the first inversion region, and
grounding the second inversion region and the semiconductor substrate,
and
wherein programming the second bit region includes
applying the positive voltage to the control gate,
applying the first negative voltage to the second inversion region, and
grounding the first inversion region and the semiconductor substrate.
27. The method of claim 26, further comprising applying a second negative voltage to the at least one sub-gate to create the first and second inversion regions in the first and second n\u2212 diffusion regions, respectively.
28. The method of claim 24, wherein the memory cell further includes a first inversion region in the first n\u2212 diffusion region and a second inversion region in the second n\u2212 diffusion region, wherein the memory cell includes a first bit region and a second bit region each for storing one bit of information, the first bit region corresponding to the first inversion region and the second bit region corresponding to the second inversion region, wherein reading the memory cell comprises reading the first bit region or the second bit region,
wherein reading the first bit region includes
applying a positive voltage to the control gate,
applying a first negative voltage to the second inversion region, and
grounding the first inversion region and the semiconductor substrate, and
wherein reading the second bit region includes
applying the positive voltage to the control gate,
applying the first negative voltage to the first inversion region, and
grounding the second inversion region and the semiconductor substrate.
29. The method of claim 28, further comprising applying a second negative voltage to the at least one sub-gate to create the first and second inversion regions in the first and second n\u2212 diffusion regions, respectively.
30. The method of claim 24,
wherein the memory cell further comprises a first insulating layer on the channel region and the first and second diffusion regions, a trapping layer on the first insulating layer, and a second insulating layer on the trapping layer,
wherein the at least one sub-gate comprises a first sub-gate over the first diffusion region and a second sub-gate over the second diffusion region,
wherein the first sub-gate, the second sub-gate, and the control gate are all on the second insulating layer,
wherein the memory cell includes a first bit region, a second bit region, a third bit region, and a fourth bit region, each of the first bit region, the second bit region, the third bit region, and the fourth bit region for storing one bit of information, the first bit region corresponding to a first part of a first portion of the trapping layer under the control gate, the second bit region corresponding to a second part of the first portion of the trapping layer, the third bit region corresponding to a first part of a second portion of the trapping layer under the first sub-gate, the fourth bit region corresponding to a second part of the second portion of the trapping layer,
wherein programming the memory cell comprises programming the first bit region, the second bit region, the third bit region, or the fourth bit region, and
wherein reading the memory cell comprises reading the first bit region, the second bit region, the third bit region, or the fourth bit region.
31. A method of operating a memory device, wherein the memory device is formed on an n\u2212 semiconductor substrate and includes a plurality of memory cells arranged in a plurality of rows each corresponding to one of a plurality of word lines and a plurality of columns each corresponding to one of a plurality of bit lines, each memory cell including a first n\u2212 diffusion region in the semiconductor substrate, a second n\u2212 diffusion region in the semiconductor substrate, a channel region defined as a portion of the semiconductor substrate between the first and second n\u2212 diffusion regions, a control gate over the channel region, and at least one sub-gate over the first and second diffusion regions, wherein the fist and second n\u2212 diffusion regions have higher doping concentrations than the semiconductor substrate, and wherein each word line connects the control gates of the memory cells in the same row, the memory device further including a plurality of p+ diffusion regions, wherein each bit line includes two of the p+ diffusion regions at the ends of the corresponding bit line, the method comprising:
at least one of resetting the memory device, erasing the memory device, programming a selected memory cell, and reading a selected memory cell.
32. The method of claim 31, wherein resetting or erasing the memory cell comprises:
applying a negative voltage on the word lines, and
grounding or applying a positive voltage to the semiconductor substrate.
33. The method of claim 31, wherein each memory cell further includes a first inversion region in the first n\u2212 diffusion region and a second inversion region in the second n\u2212 diffusion region, and each memory cell includes a first bit region and a second bit region each for storing one bit of information, the first bit region corresponding to the first inversion region and one of the two p+ diffusion regions of the corresponding bit line, and the second bit region corresponding to the second inversion region and the other of the two p+ diffusion regions of the corresponding bit line, wherein programming a selected memory cell comprises programming the first bit region or the second bit region of the selected memory cell,
wherein programming the first bit region of the selected memory cell includes
applying a positive voltage on the word line corresponding to the selected memory cell,
applying a first negative voltage on all other word lines,
applying a second negative voltage on the one of the two p+ diffusion regions of the corresponding bit line, and
grounding all other p+ diffusion regions of the memory device and the semiconductor substrate, and
wherein programming the second bit region of the selected memory cell includes
applying the positive voltage on the word line corresponding to the selected memory cell,
applying the first negative voltage on all other word lines,
applying the second negative voltage on the other of the two p+ diffusion regions of the corresponding bit line, and
grounding all other p+ diffusion regions of the memory device and the semiconductor substrate.
34. The method of claim 33, further comprising applying a third negative voltage to the sub-gate of each memory cell to create the first and second inversion regions in the corresponding first and second n\u2212 diffusion regions, respectively.
35. The method of claim 31, wherein each memory cell further includes a first inversion region in the first n\u2212 diffusion region and a second inversion region in the second n\u2212 diffusion region, and each memory cell includes a first bit region and a second bit region each for storing one bit of information, the first bit region corresponding to the first inversion region and one of the two p+ diffusion regions of the corresponding bit line, and the second bit region corresponding to the second inversion region and the other of the two p+ diffusion regions of the corresponding bit line, wherein reading a selected memory cell comprises reading the first bit region or the second bit region of the selected memory cell,
wherein reading the first bit region of the selected memory cell includes
applying a positive voltage on the word line corresponding to the selected memory cell,
applying a first negative voltage on all other word lines,
applying a second negative voltage on the other of the two p+ diffusion regions of the corresponding bit line, and
grounding all other p+ diffusion regions of the memory device and the semiconductor substrate, and
wherein reading the second bit region of the selected memory cell includes
applying the positive voltage on the word line corresponding to the selected memory cell,
applying the first negative voltage on all other word lines,
applying the second negative voltage on the one of the two p+ diffusion regions of the corresponding bit line, and
grounding all other p+ diffusion regions of the memory device and the semiconductor substrate.
36. The method of claim 35, further comprising applying a third negative voltage to the sub-gate of each memory cell to create the first and second inversion regions in the corresponding first and second n\u2212 diffusion regions, respectively.
37. The method of claim 35, wherein applying the positive voltage, applying the first negative voltage, and applying the second negative voltage comprises applying said positive, first negative, and second negative voltages such that a p-type channel is created in a portion of the channel region of the selected memory cell adjacent to the first inversion region of the selected memory cell when the first bit region of the selected memory cell is read and if the first bit region of the selected memory cell is in a programmed state, and a p-type channel is created in a portion of the channel region of the selected memory cell adjacent to the second inversion region of the selected memory cell when the second bit region of the selected memory cell is read and if the second bit region of the selected memory cell is in a programmed state.
38. The method of claim 31,
wherein each memory cell further comprises a first insulating layer on the channel region and the first and second diffusion regions, a trapping layer on the first insulating layer, and a second insulating layer on the trapping layer,
wherein the at least one sub-gate comprises a first sub-gate over the first diffusion region and a second sub-gate over the second diffusion region,
wherein the first sub-gate, the second sub-gate, and the control gate are all on the second insulating layer,
wherein each memory cell includes a first bit region, a second bit region, a third bit region, and a fourth bit region, each of the first bit region, the second bit region, the third bit region, and the fourth bit region for storing one bit of information, the first bit region corresponding to a first part of a first portion of the trapping layer under the control gate, the second bit region corresponding to a second part of the first portion of the trapping layer, the third bit region corresponding to a first part of a second portion of the trapping layer under the first sub-gate, the fourth bit region corresponding to a second part of the second portion of the trapping layer,
wherein programming the selected memory cell comprises programming the first bit region, the second bit region, the third bit region, or the fourth bit region of the selected memory cell, and
wherein reading the selected memory cell comprises reading the first bit region, the second bit region, the third bit region, or the fourth bit region of the selected memory cell.
39. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate having a first conductivity type;
forming a control gate over the semiconductor substrate;
forming at least one diffusion region having the first conductivity type in the semiconductor substrate by ion implantation, using the control gate as a mask; and
forming at least one sub-gate over the at least one diffusion region.
40. The method of claim 39, further comprising forming a first dielectric layer over the semiconductor substrate, a trapping layer over the first dielectric layer, and a second dielectric layer over the trapping layer, wherein the control gate is formed over the second dielectric layer.
41. The method of claim 40, further comprising patterning the first dielectric layer, the trapping layer, and the second dielectric layer.
42. The method of claim 41, wherein the patterning is performed before the forming of the at least one diffusion region.
43. The method of claim 41, wherein the patterning is performed after the forming of the at least one diffusion region.
44. The method of claim 39, wherein forming the at least one diffusion region includes forming the at least one diffusion region to have a higher doping concentration than the semiconductor substrate.
45. The method of claim 39, wherein providing the semiconductor substrate includes providing an n\u2212 semiconductor substrate.
46. The method of claim 39, wherein forming the at least one diffusion region includes forming a first diffusion region and a second diffusion region on opposite sides of the control gate.
47. The method of claim 46, wherein forming the at least one sub-gate includes forming one sub-gate over the first and second diffusion regions and over the control gate.
48. The method of claim 46, wherein forming the at least one sub-gate includes forming a first sub-gate over the first diffusion region and a second sub-gate over the second diffusion region.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for mitigating fouling in a wash unit used in a hydrocarbon cracking process wherein said fouling is due to the presence of polymers and deposits thereof formed by condensation of carbonyl compounds contained within a feed stream of said wash unit under alkaline conditions, the method comprising the step of:
introducing into said feed stream an effective amount of an additive consisting of:
(a) an inorganic salt of dithionite; and
(b) 6-amino caproic acid;
wherein said effective amount of additive inhibits formation of polymers of carbonyl compounds, and dissolves the polymers which are formed in spite of the inhibitory action; dissolves the polymers that exist in a caustic scrubber, and reacts with non-polymerized carbonyl compounds, low molecular weight species; high molecular weight carbonyl polymers to form the compound which is soluble in the caustic solution to thereby mitigate fouling in the wash unit,
wherein said inorganic salt of dithionite and 6-amino caproic acid are blended, and
wherein said additive scavenges the carbonyl compounds under alkaline conditions.
2. The method according to claim 1 wherein a molar ratio of carbonyl compounds to additive in the feed stream is from about 1:0.01 to about 1:25.
3. The method according to claim 1 wherein the molar ratio of carbonyl compounds to additive in the feed stream is from about 1:0.01 to about 1:1.
4. The method according to claim 1 wherein the effective amount of additive is contained within a scrubbing medium at a concentration of from about 0.5 to about 1,000,000 ppm, said scrubbing medium introduced into the feed stream at the wash unit.
5. The method according to claim 1 wherein the effective amount of additive is contained within a scrubbing medium at a concentration of from about 25 to about 200 ppm, said scrubbing medium introduced into the feed stream at the wash unit.
6. The method according to claim 1 wherein said effective amount of additive is pre-mixed with a scrubbing medium and said scrubbing medium is then introduced into the feed stream at the wash unit.
7. The method according to claim 1 wherein said inorganic salt of dithionite and 6-amino caproic acid are blended and subsequently added to the scrubbing medium before introduction of said scrubbing medium into the feed stream.
8. A method for mitigating fouling in a wash unit used in a hydrocarbon cracking process wherein said fouling is due to the presence of polymers and deposits thereof formed by condensation of carbonyl compounds contained within a feed stream of said wash unit under alkaline conditions, the method comprising the step of:
introducing into said feed stream an effective amount of an additive consisting of:
(a) an inorganic salt of dithionite, and
(b) epsilon caprolactam;
wherein said effective amount of additive inhibits formation of polymers of carbonyl compounds; dissolves the polymers which are formed in spite of the inhibitory action; dissolves the polymers that exist in a caustic scrubber; and reacts with non-polymerized carbonyl compounds, low molecular weight species, and high molecular weight carbonyl polymers to form the compound which is soluble in the caustic solution to thereby mitigate fouling in the wash unit,
wherein said inorganic salt of dithionite and epsilon caprolactam are blended, and
wherein said additive scavenges the carbonyl compounds under alkaline conditions.
9. The method according to claim 8 wherein a molar ratio of carbonyl compounds to additive in the feed stream is from about 1:0.01 to about 1:25.
10. The method according to claim 8 wherein the molar ratio of carbonyl compounds to additive in the feed stream is from about 1:0.01 to about 1:1.
11. The method according to claim 8 wherein the effective amount of additive is contained within a scrubbing medium at a concentration of from about 0.5 to about 1,000,000 ppm, said scrubbing medium introduced into the feed stream at the wash unit.
12. The method according to claim 11 wherein the effective amount of additive is contained within a scrubbing medium at a concentration of from about 25 to about 200 ppm, said scrubbing medium introduced into the feed stream at the wash unit.
13. The method according to claim 8 wherein said effective amount of additive is pre-mixed with a scrubbing medium and said scrubbing medium is then introduced into the feed stream at the wash unit.
14. The method according to claim 8 wherein said inorganic salt of dithionite and epsilon caprolactam are blended and subsequently added to the scrubbing medium before introduction of said scrubbing medium into the feed stream.
15. A method for mitigating fouling in a wash unit used in a hydrocarbon cracking process wherein said fouling is due to the presence of polymers and deposits thereof formed by condensation of carbonyl compounds contained within a feed stream of said wash unit under alkaline conditions, the method comprising the step of:
introducing into said feed stream an effective amount of an additive consisting of:
(a) an inorganic salt of dithionite; and
(b) sulfanilic acid;
wherein said effective amount of additive inhibits formation of polymers of carbonyl compounds, and reacts with non-polymerized carbonyl compounds, low molecular weight species, and high molecular weight carbonyl polymers to form the compound which is soluble in the caustic solution to thereby mitigate fouling in the wash unit,
wherein said inorganic salt of dithionite and sulfanilic acid are blended, and
wherein said additive scavenges the carbonyl compounds under alkaline conditions.
16. The method according to claim 15 wherein a molar ratio of carbonyl compounds to additive in the feed stream is from about 1:0.01 to about 1:25.
17. The method according to claim 16 wherein the molar ratio of carbonyl compounds to additive in the feed stream is from about 1:0.01 to about 1:1.
18. The method according to claim 15 wherein the effective amount of additive is contained within a scrubbing medium at a concentration of from about 0.5 to about 1,000,000 ppm, said scrubbing medium introduced into the feed stream at the wash unit.
19. The method according to claim 18 wherein the effective amount of additive is contained within a scrubbing medium at a concentration of from about 25 to about 200 ppm, said scrubbing medium introduced into the feed stream at the wash unit.
20. The method according to claim 15 wherein said effective amount of additive is pre-mixed with a scrubbing medium and said scrubbing medium is then introduced into the feed stream at the wash unit.
21. The method according to claim 15 wherein said inorganic salt of dithionite and sulfanilic acid are blended and subsequently added to the scrubbing medium before introduction of said scrubbing medium into the feed stream.