1. A Ball Grid Array (BGA) package board, comprising:
a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed;
a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed;
an insulating layer formed between the first and second external layers;
a first outer via hole to electrically connect the first and second external layers to each other; and
a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened,
wherein the solder ball pad pattern is thinner than the circuit pattern of the second external layer.
2. The BGA package board according to claim 1, further comprising:
an internal layer formed in the insulating layer, and comprising:
a plurality of circuit layers with a circuit pattern;
a plurality of insulating resin layers formed between the circuit layers; and
inner via holes to electrically connect the circuit layers to each other; and
a second outer via hole to electrically connect the external layers to the circuit layers of the internal layer.
3. The BGA package board according to claim 1, further comprising:
a gold plating layer formed on each of the wire bonding pad pattern and the solder ball pad pattern.
4. The BGA package board according to claim 3, further comprising:
nickel plating layers formed between the wire bonding pad pattern and the gold plating layer, and between the solder ball pad pattern and the gold plating layer.
5. The BGA package board according to claim 3, further comprising:
a solder ball formed on the gold plating layer of the solder ball pad pattern.
6. The BGA package board according to claim 1, wherein each of the first and second external layers comprises a material containing copper.
7. A method of manufacturing the BGA package board, comprising:
(A) providing a base plate including a first external layer, a second external layer, and an insulating layer provided between the first and second external layers;
(B) forming a pattern including a circuit pattern and a wire bonding pattern on the first external layer, and forming a pattern including a circuit pattern and a solder ball pad pattern on the second external layer;
(C) coating a solder resist on each of the first and second external layers, and forming a solder resist pattern which is opened at portions corresponding to the wire bonding pad pattern and the solder ball pad pattern; and
(D) partially etching the solder ball pad pattern of the second external layer.
8. The method according to claim 7, further comprising:
(E) forming a first outer via hole on the base plate, after the (A) step of providing the base plate; and
(F) forming a copper plating layer on each of the first and second external layers of the base plate and sidewalls of the first outer via hole.
9. The method according to claim 7, further comprising:
(E) forming a nickel plating layer on each of the wire bonding pattern and the solder ball pad pattern, after the (D) step of partially etching the solder ball pad pattern of the second external layer;
(F) forming a gold plating layer on the nickel plating layer formed on each of the wire bonding pad pattern and the solder ball pad pattern; and
(G) forming solder balls on the gold plating layer with the solder ball pad pattern.
10. The method according to claim 7, wherein the (D) step of partially etching the solder ball pad pattern of the second external layer comprises:
(D-1) coating an etching resist on the solder resist of the second external layer, and exposing and developing the etching resist, thus forming an etching resist pattern so that a portion corresponding to the solder ball pad pattern is opened;
(D-2) partially etching the solder ball pad pattern, using the etching resist pattern; and
(D-3) removing the etching resist.
11. The method according to claim 10, wherein the (D-2) step of partially etching the solder ball pad pattern comprises:
partially etching the solder ball pad pattern using a wet etching method including a spray etching method.
12. The method according to claim 10, wherein the (D-2) step of partially etching the solder ball pad pattern comprises:
partially etching the solder ball pad pattern using a dry etching method including a plasma etching method.
13. The method according to claim 10, wherein the etching resist comprises a photo resist material.
14. The method according to claim 7, wherein the base plate comprises:
an internal layer formed in the insulating layer, and comprising:
a plurality of circuit layers with a circuit pattern;
a plurality of insulating resin layers formed between the circuit layers; and
inner via holes to electrically connect the circuit layers to each other; and
a second outer via hole to electrically connect the external layers to the circuit layers of the internal layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit (IC) chip comprising:
a substrate layer;
a first insulating layer on said substrate layer;
a first semiconductor layer on said first insulating layer, transistors being formed from said first semiconductor layer and connected together into circuit elements in a circuit layer;
a second insulating layer attached to said first semiconductor layer;
a second semiconductor layer on said second insulating layer, transistors being formed from said second semiconductor layer, and connected together into an array of circuit elements in a circuit layer, wherein a majority of IC chip elements are located on said first semiconductor layer; and
a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on and extending from one of said circuit elements on said first semiconductor layer and said second semiconductor layer, ones of said circuit elements on said first semiconductor layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second semiconductor layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC;
wherein said circuit elements on said SOI CMOS circuit layer include combinational logic and said array of circuit elements is a CMOS driver grid, selected drivers of said CMOS driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer.
2. An IC chip as in claim 1, wherein said first semiconductor layer is a silicon layer and said substrate layer, said first insulating layer and said silicon layer are layers in a silicon on insulator (SOI) CMOS circuit layer.
3. An IC chip as in claim 2, wherein said SOI CMOS circuit layer further comprises a wiring layer above said silicon layer, said transistors being connected together by wiring in said wiring layer and said IC further comprises a polymeric adhesive layer bonding said second insulating layer and said SOI CMOS circuit layer, said polymeric adhesive layer attaching said second semiconductor layer to said SOI CMOS circuit layer, said plurality of interlayer connection channels extending linearly between said ones and said corresponding ones.
4. An IC chip as in claim 2, further comprising a wiring layer disposed between said SOI CMOS circuit layer and said second semiconductor layer, another end of ones of said plurality of interlayer connections being connected to wires on said wiring layer.
5. An IC chip as in claim 4, wherein said second semiconductor layer includes a clock distribution for said SOI CMOS circuit layer.
6. An IC chip as in claim 5, wherein said clock distribution includes a plurality of CMOS clock drivers.
7. An IC as in claim 4, wherein said second insulator layer and said second semiconductor layer are layers in a second SOI CMOS circuit layer.
8. A CMOS integrated circuit (IC) chip comprising:
an SOI circuit layer comprising:
a semiconductor substrate layer;
an insulating layer on said substrate layer, and
a silicon layer on said insulating layer, Field Effect Transistors (FETs) being formed in said silicon layer and connected together into circuit elements in a circuit layer;
a second insulating layer attached to said SOI circuit layer;
a CMOS driver grid in a second silicon layer on said second insulating layer, wherein a majority of IC chip elements are located on said SOI circuit layer; and
a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on and extending from one of said circuit elements in said SOI circuit layer and said second silicon layer, ones of said circuit elements on said SOI circuit layer being connected through said plurality of interlayer connection channels to corresponding ones of said array of circuit elements, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said CMOS IC; and
wherein said circuit elements on said SOI circuit layer include combinational logic, selected drivers of said CMOS driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer.
9. A CMOS IC chip as in claim 8, wherein said SOI circuit layer further comprises a wiring layer above said silicon layer, said FETs being connected together by wiring in said wiring layer and said IC further comprises a polymeric adhesive layer bonding said second insulating layer and said SOI circuit layer, said polymeric adhesive layer attaching said second silicon layer to said SOI circuit layer, said plurality of interlayer connection channels extending linearly between said ones and said corresponding ones.
10. A CMOS IC chip as in claim 8, further comprising a wiring layer attached between said SOI circuit layer and said second silicon layer, another end of ones of said plurality of interlayer connections being connected to wires on said wiring layer.
11. An integrated circuit (IC) comprising:
a plurality of circuit layers adhesively bonded to one another in a stack and including at least a first circuit layer and a second circuit layer of transistors connected together into circuit elements, wherein said first circuit layer is a silicon on insulator (SOI) CMOS circuit layer, said circuit elements on said SOI CMOS circuit layer comprise combinational logic said second circuit layer includes an array of active circuit elements and said array of active circuit elements is a CMOS driver grid, selected drivers of said driver grid being power up buffers for corresponding combinational logic gates on said SOI CMOS circuit layer;
a plurality of said circuit elements on said second circuit layer being disposed directly above a plurality of said circuit elements on first layer; and
a plurality of interlayer connection channels, each interlayer connection channel having an end terminating on one of said circuit elements on said first layer and said second layer, ones of said circuit elements on said first layer being connected through said plurality of interlayer connection channels to corresponding ones of said circuit elements on said second layer, connection of said ones to said corresponding ones forming a three dimensional (3D) higher level circuit element within said IC.