1. A method for handling email messages, the method comprising:
receiving, from a first mobile device of a user, a request for email messages that are associated with an email account, wherein the request does not specify use of any particular profile or any particular filter criteria;
wherein the email account is associated with multiple profiles;
wherein each profile of the multiple profiles is associated with a different set of filter criteria;
in response to the request, performing particular steps comprising:
identifying a first active profile that is associated with the first mobile device;
identifying a particular set of filter criteria that is associated with the first active profile of the multiple profiles associated with the email account;
wherein the multiple profiles include a second active profile that is associated with a second mobile device of the user;
wherein the second mobile device is separate from the first mobile device;
applying the particular set of filter criteria to a set of email messages to identify selected email messages that satisfy the filter criteria in the particular set of filter criteria, thereby filtering email messages;
wherein the filtering is performed based on an active profile that is associated with the first mobile device that is requesting email messages; and
transmitting the selected email messages to the first mobile device.
2. The method of claim 1, wherein the particular set of filter criteria includes an urgency associated with each email message.
3. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 2.
4. The method of claim 1, wherein the particular set of filter criteria includes a source associated with each email message.
5. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 4.
6. The method of claim 1, wherein the particular set of filter criteria includes a date associated with each email message.
7. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 6.
8. The method of claim 1, wherein the particular set of filter criteria is specified by the user.
9. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 8.
10. The method of claim 1 further comprising:
receiving a request to delete one of the selected email messages; and
deleting the requested email message from the set of email messages.
11. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 10.
12. The method of claim 1, further comprising:
receiving a request to change the particular set of filter criteria; and
updating the particular set of filter criteria applied to the set of email messages.
13. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 12.
14. The method of claim 1, wherein the received request for email messages includes information identifying an email account associated with the user.
15. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 14.
16. The method of claim 1 wherein the received request for email messages is communicated from the mobile device using the Internet Messaging Access Protocol.
17. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 16.
18. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 1.
19. The method of claim 1, wherein:
the multiple profiles include a plurality of profiles selectable by the first mobile device;
one of the plurality of profiles selectable by the first mobile device is currently designated as an active profile for the first mobile device; and
the step of identifying the particular set of filter criteria includes identifying filter criteria associated with the currently designated active profile for the first mobile device.
20. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 19.
21. The method of claim 1, wherein the request is a user-initiated request.
22. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 21.
23. The method of claim 1, wherein:
the first active profile is a sole active profile for the first mobile device at a same time that the second active profile is a sole active profile for the second mobile device; and
the first active profile and the second active profile both are associated with the email account.
24. A volatile or non-volatile computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to perform the method recited in claim 23.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A shifter circuit comprising:
a high voltage buffer stage comprising:
multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack, the transistor stack being connected between a voltage level being shifted to and an input voltage; and
an inverter comprising multiple inputs and an output, individual inverter inputs being connected to a respective intermediate node of the transistor stack;
a low voltage buffer stage having an input connected to said input voltage, and an output, the low voltage buffer stage being operably connected to the high voltage buffer stage and being connected between a voltage level being shifted away from and a lower voltage; and
an output buffer stage driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.
2. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the p-channel devices are connected between the n-channel devices and the voltage level being shifted to.
3. The shifter circuit of claim 1, wherein the inverter comprises p-channel and n-channel devices.
4. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device.
5. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and wherein the said inverter inputs are connected across at least one common p-channel device.
6. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and wherein the input of the inverter’s p-channel device is connected to an intermediate node between two p-channel devices.
7. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and wherein the input of the inverter’s p-channel device is connected to the intermediate node between the two p-channel devices, and wherein the input of the inverter’s n-channel device is connected between the intermediate node between the p-channel device and the n-channel device.
8. The shifter circuit of claim 1, wherein the transistors of the transistor stack comprise gatedrain connected MOSFETs.
9. A shifter circuit comprising:
a high voltage buffer stage comprising:
multiple transistor stacks, each of which comprising multiple transistors having a plurality of intermediate nodes connecting individual transistors along a respective stack, each transistor stack being connected between a voltage level being shifted to and an input voltage; and
multiple inverters each of which comprising multiple inputs and an output, each inverter being connected with an individual respective one of the transistor stacks, individual inverter inputs being connected to a respective intermediate node of its connected transistor stack;
a low voltage buffer stage having an input connected to said input voltage and an output, the low voltage buffer stage being operably connected to the high voltage buffer stage and being connected between a voltage level being shifted away from and a lower voltage; and
an output buffer stage driven by the output of a high voltage buffer stage inverter and the output of the low voltage buffer stage.
10. The shifter circuit of claim 9, wherein each transistor stack comprises p-channel and n-channel devices, and wherein the p-channel devices of a stack are connected between the n-channel devices of the stack and the voltage level being shifted to.
11. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices.
12. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:
one input of its associated inverter is connected to an intermediate node between two p-channel devices, and
another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device.
13. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:
one input of its associated inverter is connected to an intermediate node between two p-channel devices,
another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and
wherein the said inverter inputs are connected across at least one common p-channel device.
14. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:
one input of its associated inverter is connected to an intermediate node between two p-channel devices,
another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and
wherein the input of the inverter’s p-channel device is connected to the intermediate node between the two p-channel devices.
15. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:
one input of its associated inverter is connected to an intermediate node between two p-channel devices,
another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and
wherein the input of the inverter’s p-channel device is connected to the intermediate node between the two p-channel devices, and wherein the input of the inverter’s n-channel device is connected between the intermediate node between the p-channel device and the n-channel device.
16. The shifter circuit of claim 9, wherein the transistors of each transistor stack comprise gatedrain connected MOSFETs.
17. The shifter circuit of claim 9, wherein said low voltage buffer stage comprises multiple low voltage buffer stages cascaded together.
18. A method comprising:
supplying a voltage level away from which a shift is desired;
supplying a voltage level to which a shift is desired;
supplying an input voltage; and
shifting the input voltage, using said voltage levels and a circuit comprising:
a high voltage buffer stage comprising:
multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack, the transistor stack being connected between the voltage level being shifted to and the input voltage; and
an inverter comprising multiple inputs and an output, individual inverter inputs being connected to a respective intermediate node of the transistor stack;
a low voltage buffer stage having an input connected to said input voltage and an output, the low voltage buffer stage being operably connected to the high voltage buffer stage and being connected between said voltage level being shifted away from and a lower voltage; and
an output buffer stage driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.
19. The method of claim 18, wherein said high voltage buffer stage comprises multiple transistor stacks and multiple inverters, each transistor stack being associated with an inverter.
20. The method of claim 18, wherein said low voltage buffer stage comprises multiple low voltage buffer stages cascaded together.