1. A non-volatile NAND Flash memory cell comprising:
a substrate having a first doped materials;
a lightly second doped junction regions near the said substrate surface;
a stacked insulator-polysilicon-tunnel oxide of the memory cell overlaying the second doped surface junction region of the memory cell;
a control gate overlaying a insulator-polysilicon-tunnel oxide of the memory cell; and
a self aligned spacer in the side wall of a control gate and a insulator-polysilicon-tunnel oxide of the memory cell in order to isolate the adjacent control gates.
2. The memory cell structure of claim 1 wherein said the first control gate and the self-aligned control gate is formed as polysilicon, or polycide or both combinations of polysilicon and polycide thereon.
3. The memory cell structure of claim 1 wherein said the polysilicon of the stacked insulator-polysilicon-tunnel oxide is lightly doped.
4. The memory cell structure of claim 1 wherein said the self-aligned spacer is composed of a oxide.
5. A string of non-volatile NAND Flash memory cells comprising:
a substrate having a first doped materials;
forming highly second doped source and drain junction regions overlaying the first doped substrate;
forming a first dielectric material on the surface of said the substrate;
forming a selective gates between the second highly doped region on the surface of said the substrate;
forming a second lightly doped junction regions overlaying the said first doped substrate;
forming a control gate overlaying the a stacked insulator-polysilicon-tunnel oxide of the memory cell overlaying the second doped surface junction region of the memory cell;
forming self aligned spacers in the side walls of a control gate and a stacked insulator-polysilicon-tunnel oxide of the memory cell overlaying the substrate of the memory cell; and
forming a secondary dielectric materials between the select gate and the control gates of the memory cell.
6. The string of a NAND memory cells structure of claim 5 wherein said the first dielectric material is oxide or oxy-nitride, or dielectric material.
7. The string of a NAND memory cells structure of claim 5 wherein said the control gate is formed as polysilicon, or polycide or combinations of both polysilicon and polycide thereon.
8. A method making a series of NAND memory cells structure comprising:
forming, through masking steps and ion implantation processes, a first n-well in a semiconductor substrate, forming a first p-well overlaying the first n-well, in a semiconductor substrate;
forming a non-volatile device region by removing either deposited material or materials or grown oxide layer down to surface of the substrate using a mask step;
forming a low doped surface junction for the said non-volatile device region by ion implantation;
forming a first spacer above the body region and adjacent said first polysilicon layer to isolate said memory region;
forming a stacked insulator-polysilicon-tunnel oxide on the surface of the substrate;
forming a second polysilicon layer above said the stacked insulator-polysilicon-tunnel oxide;
forming a first NAND control gate by etching above said the second polysilicon, and said the stacked insulator-polysilicon-tunnel oxide using mask step processes;
forming a second spacer above the first control gate region and adjacent said the first control gate on the stacked insulator-polysilicon-tunnel oxide;
forming a stacked insulator-polysilicon-tunnel oxide overlaying the entire said substrate;
forming a third polysilicon overlaying the stacked insulator-polysilicon-tunnel oxide overlaying the entire said substrate;
forming a second self-aligned NAND control gate by etch back process for the said entire bodies on the substrate.
9. The method of claim 8 wherein said the width of the self aligned control gate is determined by the control gate drawn space minus two times the second spacer width.
10. The method making a series of NAND memory cells structure comprising of claim 8 wherein said the width of the self aligned control gate is approximately the same as the width of the first control gate by adjusting the art work drawing in the layout design.
11. The method making a series of NAND memory cells structure comprising of claim 8 wherein said the first, the second and the third polysilicon is doped with in-situ method; and the polysilicon is combination with polycide or silicide.
12. The method making a series of NAND memory cells structure comprising of claim 8 wherein underneath said the second spacer in the region of the NAND cell region is become as the source and drain of the NAND Flash cells said lightly doped during said the ion implantation.
13. The method making a series of NAND memory cells structure comprising of claim 8 wherein underneath said the second spacer in the region of the NAND cell region is become as the source and drain of the NAND Flash cells said lightly doped during said the ion implantation.
14. The memory cell of claim 8 wherein said substrate is a p-type region formed in an n-well.
15. A method of making a string of NAND memory cells structure comprising:
forming at least two isolation regions in a semiconductor substrate;
forming, through masking steps and ion implantation processes, a first n-well in a semiconductor substrate, forming a first p-well overlaying the first n-well, forming a second highly doped p-well near the first n-well and the first p-well, forming a second highly doped p-well near the first n-well and the first p-well, forming a second highly doped n-well, and forming a third highly doped n-well regions to define a body region;
forming a first oxide layer or a third oxide layer by using several masking steps above the body region;
forming a first polysilicon layer above said first oxide layer and above said third oxide layer;
forming a non-volatile device region by removing the first polysilicon, the first oxide and the third oxide layer on the substrate using a mask step;
forming a low doped surface junction for the said non-volatile device region by ion implantation;
forming a first spacer above the body region and adjacent said first polysilicon layer;
forming a stacked insulator-polysilicon-tunnel oxide on said the non-volatile device region;
forming a second polysilicon layer above said the stacked insulator-polysilicon-tunnel oxide;
forming a first NAND control gate by etching above said the second polysilicon, and said the stacked insulator-polysilicon-tunnel oxide using mask step processes;
forming a second spacer above the first control gate region and adjacent said the first control gate and the stacked insulator-polysilicon-tunnel oxide on the substrate;
forming a stacked insulator-polysilicon-tunnel oxide overlaying the entire said substrate;
forming a third polysilicon overlaying the stacked oxide-nitride-oxide overlaying the entire said substrate;
forming a second self-aligned NAND control gate by etch back process for the said entire bodies on the substrate;
forming transistor gates for the low voltages and high voltage over the said the first oxide and the third oxide.
16. The method making a string of NAND memory cells structure of claim 15 wherein said the width of the self aligned control gate is determined by the control gate drawn space minus two times the second spacer width.
17. The method making a string of NAND memory cells structure of claim 15 wherein said the width of the self aligned control gate is approximately the same as the width of the first control gate by adjusting the art work drawing in the layout design.
18. The method making NAND Flash memory comprising string of a NAND memory cells structure of claim 15 wherein said the first, the second and the third polysilicon is doped with in-situ method; and the polysilicon is combination with polycide or silicide.
19. The method making NAND Flash memory comprising string of a NAND memory cells structure of claim 15 wherein underneath said the second spacer in the region of the NAND cell region is become as the source and drain of the NAND Flash cells said lightly doped during said the ion implantation.
20. The memory cell of claim 15 wherein said substrate is a p-type region formed in an n-well.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A connector connected with a circuit board of a portable electronic device, the circuit board having a plurality of conductive pads formed thereon, the connector comprising:
a housing including a top wall, sidewalls, and a completely open bottom end, the top wall and the sidewalls together defining a cavity communicating with the open end of the housing; and
a plurality of conducting terminals proximate the completely open bottom end of the housing, the conducting terminals being mounted in and extending from at least one sidewall of the housing;
wherein the conducting terminals are electronically and mechanically connected with the conductive pads, and thereby the completely open end of the housing is fixed to the circuit board.
2. The connector as described in claim 1, wherein the circuit board has a board hole formed therethrough, the completely open end of the housing being inserted within the board hole of the circuit board.
3. The connector as described in claim 2, wherein the conductive pads on the circuit board are provided around the board hole, the distribution of the conducting terminals corresponding to the distribution of the conductive pads.
4. The connector as described in claim 3, wherein each terminal further including an outer portion and an inner portion, the outer portion of each terminal extends outwardly from the at least one sidewall of the housing, the outer portion of the each terminal is welded or soldered to a respective conductive pad on the circuit board, and the inner portion of each terminal projects inwardly of the sidewall of the housing.
5. The connector as described in claim 1, the sidewalls have at least one latching mechanism associated therewith, and each latching mechanism is configured for fixing the connector with the functional module.
6. The connector as described in claim 5, wherein each latching mechanism is an elastic cantilever body provided in the at least one sidewall of the housing, each elastic cantilever body being configured for snap-fitting into a corresponding slot defined in the functional module.
7. A portable electronic device, comprising:
a circuit board having a board hole therethrough and having a plurality of conductive pads formed thereon, around the board hole;
a functional module including a plurality of conducting portions; and
a connector including a housing and a plurality of conducting terminals, the housing comprising a top wall and sidewalls, the top wall and the sidewalls together define an open end and a cavity communicating with the open end, the conducting terminals are provided in the housing, near the open end thereof;
wherein the open end of the housing is fixed to the circuit board extends into the board hole, the conducting terminals are electronically connected to the conductive pads, the connector is configured so as to hold the functional module in the cavity of the connector, and the conducting portions are electronically connected with the respective conductive pads of the circuit board via conducting terminals of the connector.
8. The portable electronic device as described in claim 7, wherein the distribution of the conducting terminals corresponds to the distribution of the conductive pads.
9. The portable electronic device as described in claim 8, wherein the terminals pierce through the sidewall of the housing and extend outward from the housing, a part of the terminals outside the housing is welded to the conductive pads on the circuit board; the part of the terminals inside the housing are electronically connected with the conducting portions.
10. The portable electronic device as described in claim 7, a gripping mechanism is used for fixing the connector to the functional module.
11. The portable electronic device as described in claim 10, wherein the gripping mechanism is at least one elastic body provided in the sidewall of the housing and at least one slot defined on the functional module, the at least one elastic body is inserted into the at least one slot when assembled.
12. A connector connected with a circuit board of a portable electronic device, the circuit board having a plurality of conductive pads formed thereon, the connector comprising:
a housing including a top wall and sidewalls, the top wall and the sidewalls together defining an open end of the housing and a cavity, the cavity being configured for receiving a functional module of the portable electronic device therein;
a plurality of conducting terminals provided near the open end of the housing, the conducting terminals being mounted in and extending from at least one sidewall of the housing; and
a gripping mechanism used for fixing the housing with the functional module;
wherein the conducting terminals are electronically and mechanically connected with the conductive pads, and thereby the open end of the housing is fixed to the circuit board.
13. The connector as described in claim 12, wherein the circuit board has a board hole formed therethrough, the open end of the housing being inserted within the board hole of the circuit board.
14. The connector as described in claim 13, wherein the conductive pads on the circuit board are provided around the board hole, the distribution of the conducting terminals corresponding to the distribution of the conductive pads.
15. The connector as described in claim 14, wherein the terminals are mounted within the sidewall of the housing, each terminal further including an outer portion and an inner portion, the outer portion of each terminal extends outwardly from at least one sidewall, the outer portion of the each terminal is welded or soldered to a respective conductive pad on the circuit board, and the inner portion of each terminal projects inwardly of the at least one sidewall.
16. The connector as described in claim 12, wherein the functional module has a plurality of conducting portions formed thereon, the conducting terminals each include an inner portion, and each respective inner portion is configured for electronically connecting with a corresponding conducting portion.
17. The connector as described in claim 12, wherein the gripping mechanism is at least one latching mechanism associated with at least one of the sidewalls.
18. The connector as described in claim 17, wherein each latching mechanism is an elastic cantilever body provided in the at least one sidewall of the housing, each elastic cantilever body being configured for snap-fitting into a corresponding slot defined in the functional module.