1. A compound of formula (I):
wherein:
Q is a group of formula Q1, Q2, Q3, Q4, Q5, or Q6:
Z is H or OH;
Y is \u2014(CH2)n\u2014 wherein n is an integer of 1 to 12 or is a divalent group of formula Y1:
wherein:
A1 and A2 are, each independently, absent or are selected from the group consisting of (C1-C6)alkylene, (C3-C8)cycloalkylene, and (C3-C8)heterocycloalkylene;
B is absent or is selected from the group consisting of (C3-C8)cycloalkylene, (C3-C8)heterocycloalkylene, arylene, and heteroarylene or is a group of formula B1
C is absent or is selected from the group consisting of \u2014O\u2014, \u2014OCO\u2014, \u2014C(O)O\u2014, \u2014S\u2014, \u2014S(O)\u2014, \u2014S(O)2\u2014, and \u2014N(R4)\u2014 or is one of the following groups C1-C10:
wherein R4 is H or is selected from the group consisting of (C1-C8)alkyl, (C3-C8)cycloalkyl, (C3-C8)heterocycloalkyl, aryl, and heteroaryl;
D is selected from the group consisting of (C1-C12)alkylene, (C2-C12)alkenylene, and (C2-C6)alkynylene, optionally substituted by one or more (C1-C6)alkyl;
R is \u2014H or (C1-C4)alkyl;
X is \u2014O\u2014 or \u2014S\u2014;
R1 is H or is selected from the group consisting of (C3-C8)cycloalkyl, aryl, heteroaryl, aryl(C1-C6)alkyl, heteroaryl(C1-C6)alkyl, and (C3-C8)cycloalkyl(C1-C6)alkyl, optionally substituted by one or more (C1-C4)alkoxy;
R2 is selected from the group consisting of (C3-C8)cycloalkyl, aryl, heteroaryl, aryl(C1-C6)alkyl, heteroaryl(C1-C6)alkyl, and (C3-C8)cycloalkyl(C1-C6)alkyl, optionally substituted by one or more halogen atoms or (C1-C4)alkoxy;
R3 is H or is selected from the group consisting of \u2014OH, hydroxy(C1-C6)alkyl, \u2014N(R5R6), and \u2014N(R5)CO(R6);
R5 and R6 are independently H or (C1-C6)alkyl;
or a pharmaceutically acceptable salt thereof.
2. A compound or salt according to claim 1, wherein R1 is H or is selected from the group consisting of (C3-C8)cycloalkyl, aryl, heteroaryl, and aryl(C1-C6)alkyl; R2 is selected from the group consisting of (C3-C8)cycloalkyl, aryl, heteroaryl, aryl(Cj\u2014C6)alkyl, heteroaryl(C1-C6)alkyl, and (C3-C8)cycloalkyl(C1-C6)alkyl; R3 is H or is selected from the group consisting of \u2014OH, hydroxy(C1-C6)alkyl, \u2014N(R5R6), and \u2014N(R5)CO(R6); X is \u2014O\u2014 or \u2014S\u2014; and R is \u2014H or (C1-C4)alkyl.
3. A compound or salt according to claim 2, wherein R1 is H or is selected from the group consisting of cyclobutyl, cyclopentyl, phenyl, benzyl, cycloheptyl, thienyl, and cyclohexyl; R2 is selected from the group consisting of phenyl, thienyl, cyclohexyl, triphenylmethyl, chlorophenyl, methoxyphenyl, and fluorophenyl; R3 is H or is selected from the group consisting of \u2014OH, \u2014NH2, \u2014CH2OH, \u2014NHCOCH3; X is \u2014O\u2014; and R is H or \u2014CH3.
4. A compound or salt according to claim 1, wherein Y is \u2014(CH2)n\u2014 wherein n is an integer of 1 to 12 or is a group of formula Y1:
wherein:
A1 and A2 are, each independently, absent or are selected from the group consisting of (C1-C6)alkylene, (C3-C8)cycloalkylene, and (C3-C8)heterocycloalkylene; B is absent or is selected from the group consisting of (C3-C8)cycloalkylene, (C3-C8)heterocycloalkylene, arylene, and heteroarylene or is a group of formula B1:
C is absent or is selected from the group consisting of \u2014O\u2014, \u2014OCO\u2014, \u2014C(O)O\u2014, \u2014S\u2014, \u2014N(R4)\u2014 or is one of the following C1-C10 groups:
wherein R4 is H or is selected from the group consisting of (C1-C8)alkyl, (C3-C8)cycloalkyl, (C3-C8)heterocycloalkyl, aryl, and heteroaryl; D is selected from the group consisting of (C1-C12)alkylene, (C2-C12)alkenylene, and (C2-C6)alkynylene; Z is \u2014H or \u2014OH and Q is a group of formula Q1, Q2, Q3, Q4, Q5 or Q6:
5. A compound or salt according to claim 4, wherein Y is \u2014(CH2)n\u2014, Z is OH and Q is a group of formula Q1:
according to formula (IA):
6. A compound or salt according to claim 5, wherein n is 4, 5, 6, 7 or 8.
7. A compound or salt according to claim 1, wherein Y is a divalent group of
wherein A1 is (C3-Cg)cycloalkylene, B and C are absent, D is (C1-C12)alkylene, Z is OH and Q is a group of formula Q1:
according to formula (IB), wherein (C3-C8)cycloalkylene is represented by \u201ccy\u201d
8. A compound or salt according to claim 4, wherein A1 is piperinyl and D is hexylene.
9. A compound or salt according to claim 1, wherein Y is \u2014(CH2)n\u2014, Z is H and Q is a group of formula Q3:
according to formula (IC):
10. A compound or salt according to claim 9, wherein n is 8.
11. A pharmaceutical composition, comprising a compound or salt according to claim 1 and one or more pharmaceutically acceptable carriers andor excipients.
12. A method for the prevention andor treatment of a broncho-obstructive or inflammatory disease, comprising administering an effective amount of a compound or salt according to claim 1 to a subject in need thereof.
13. A method for the prevention andor treatment of asthma, chronic bronchitis, or chronic obstructive pulmonary disease, comprising administering an effective amount of a compound or salt according to claim 1 to a subject in need thereof.
14. A combination of a compound or salt according to claim 1 and one or more active ingredients selected from the group consisting of a corticosteroid, a P38 MAP kinase inhibitor, a IKK2 inhibitor, a HNE inhibitor, a PDE4 inhibitor, a leukotriene modulator, a NSAID, and a mucus regulator.
15. A pharmaceutical composition according to claim 11, which is in a form suitable to be administered by inhalation.
16. A pharmaceutical composition according to claim 15 which is an inhalable powder, a propellant-containing metering aerosol, or a propellant-free inhalable formulation.
17. A device comprising a pharmaceutical composition according to claim 15, which is a single- or multi-dose dry powder inhaler, a metered dose inhaler, or a soft mist nebulizer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a memory cell array including a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages;
a second storage unit into which a page address, of the plurality of page addresses, stored in the first storage unit is loaded; and
a control circuit configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, perform the program operation and update the second storage unit with the externally inputted page address if the externally inputted page address is greater than the page address, transfer the externally inputted page address to the first storage unit if the program operation is canceled, read the second storage unit after the program operation is terminated to determine whether or not a delay time has occurred, and determine that the delay time has occurred if a page address corresponding to a last programmed page is stored in the second storage unit and that the delay time has not occurred if the page address corresponding to the last programmed page is not stored in the second storage unit.
2. The semiconductor device of claim 1, further comprising:
peripheral circuits configured to perform the program operation on a page corresponding to the externally inputted page address.
3. The semiconductor device of claim 2, wherein the peripheral circuits include:
a voltage generation circuit configured to generate voltages for the program operation in response to a program signal output from the control circuit;
an X decoder configured to transfer the voltages, generated by the voltage generation circuit, to word lines of a selected memory block, of the plurality of memory blocks, in response to a row address output from the control circuit;
a Y decoder configured to exchange data through bit lines coupled to the memory cell array in response to a column address output from the control circuit;
an inputoutput buffer configured to exchange the data with the Y decoder in response to an inputoutput signal output from the control circuit;
an inputoutput driver configured to externally receive data or externally output the data transferred from the inputoutput buffer;
a global data buffer configured to receive global data corresponding to a page address from the inputoutput buffer and output the global data as the page address; and
an address storage circuit, including the second storage unit, and configured to receive the page address from the global data buffer, store the page address in the second storage unit, and transfer a last stored page address to the control circuit when the program operation is completed.
4. The semiconductor device of claim 3, further comprising:
a page address check circuit configured to output a delay signal if a delay time occurs for a predetermined period of time during the program operation; and
a power sensing circuit configured to determine if power to the semiconductor device turns off, and output a power off signal to the control circuit if the power is supplied to the semiconductor device to perform a subsequent operation.
5. The semiconductor device of claim 4, wherein the page address check circuit outputs the delay signal if the page address is not stored in the second storage unit after the program operation is completed or terminated.
6. The semiconductor device of claim 4, wherein the control circuit reads the second storage unit to find a memory block in an erase state and selects the memory block to perform a new program operation thereon if the power off signal is outputted.
7. The semiconductor device of claim 6, wherein the power sensing circuit selects the memory block to perform the new program operation thereon and is subsequently reset.
8. The semiconductor device of claim 4, wherein the control circuit controls the peripheral circuits to:
erase data stored in the first storage unit if the program operation is terminated, and
transfer the page address stored in the second storage unit to the first storage unit.
9. The semiconductor device of claim 1, wherein the control circuit controls the peripheral circuits to:
reset information about a selected memory block in the second storage unit during an erase operation,
perform the erase operation, and
transfer the page address stored in the second storage unit to the first storage unit.
10. The semiconductor device of claim 1, wherein the control circuit controls the peripheral circuits to:
read a selected page of the plurality of pages and,
transfer the page address, stored in the second storage unit, to the first storage unit during a read operation.
11. A method of operating a semiconductor device, the method comprising:
loading a first page address, stored in a first storage unit, into a second storage unit;
updating the first page address, stored in the second storage unit, with a second page address, input from an external device;
performing a subsequent program operation if the second page address is greater than the first page address;
canceling the subsequent program operation if the second page address is less than or equal to the first page address;
transferring the second page address, stored in the second storage unit, to the first storage unit if the program operation is canceled;
reading the second storage unit after the program operation is terminated to determine whether or not a delay time has occurred; and
determining that the delay time has occurred if a page address corresponding to a last programmed page is stored in the second storage unit and that the delay time has not occurred if the page address corresponding to the last programmed page is not stored in the second storage unit.
12. The method of claim 11, further comprising:
loading the first page address, stored in the first storage unit, into the second storage unit; and
checking a power state of the semiconductor device.
13. The method of claim 12, wherein if, as a result of the checking a power state of the semiconductor device, it is determined that a sudden power off occurred in a previous operation, then the second storage unit will be read to find a memory block in an erase state, and the memory block in the erase state will be selected as a memory block on which the subsequent program operation will be performed.