1. An apparatus comprising:
a frequency acquisition loop to lock a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock, the frequency acquisition loop generating first and second feedback clocks from the VCO clock;
a data lock phase loop coupled to the frequency acquisition loop to generate a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock, the driving signal controlling the multi-band VCO in a data phase lock mode; and
a lock detect controller coupled to the frequency acquisition loop to detect a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock.
2. The apparatus of claim 1 wherein the frequency acquisition loop comprises:
a divider to divide the VCO clock to provide the first and second feedback clocks;
a loop filter coupled to the multi-band VCO to filter a control signal, the filtered control signal controlling the multi-band VCO;
a loop multiplexer coupled to the loop filter to select the control signal from a common mode signal, a frequency error signal, and the driving signal based on a multiplexer select code.
a phase frequency detector (PFD) and a charge pump coupled to the loop multiplexer and the divider to provide the frequency error signal based on the reference clock and the first feedback clock.
3. The apparatus of claim 2 wherein the lock detect controller comprises:
a comparator to compare the first feedback clock and the reference clock, the comparator generating a lock signal when a frequency difference of first feedback clock and the reference clock is less than a threshold value;
a control circuit coupled to the comparator to generate the multiplexer select code and band select code to the multi-band VCO based on the lock signal and configuration bits; and
a configuration register coupled to the control circuit to provide the configuration bits.
4. The apparatus of claim 3 wherein the control circuit comprises:
a frequency coarse tuning circuit to select a zone lock frequency band from a plurality of frequency bands of the multi-band VCO, the zone lock frequency band having a smallest frequency difference between the first feedback clock and the reference clock;
a frequency fine tuning circuit coupled to the frequency coarse tuning circuit to assert or de-assert the frequency lock condition using the selected zone lock frequency band; and
a data phase lock control circuit coupled to the frequency fine tuning circuit to assert or de-assert the data lock condition.
5. The apparatus of claim 3 wherein the control circuit generates the multiplexer select code to the loop multiplexer to select the common mode signal, a frequency error signal, and the driving signal corresponding to the frequency coarse tuning circuit, the frequency fine tuning circuit, and the data phase lock control circuit, respectively.
6. The apparatus of claim 1 wherein the data lock phase loop comprises:
a decision-directed phase detector (DDPD) coupled to a finite impulse response (FIR) filter clocked by the second feedback clock to generate the phase error signal using a minimum mean square error (MMSE) criteria, the phase error signal including first and second phase error signals; and
a linear trans-conductor coupled to the DDPD to generate a differential current from the phase error signal, the differential current corresponding to the driving signal that controls the multi-band VCO.
7. The apparatus of claim 6 wherein the DDPD comprises:
a first phase error circuit to generate a first re-timed amplitude error and a first re-timed binary slope from a first data sample from the FIR filter;
a second phase error circuit to generate a second re-timed amplitude error and a second re-timed binary slope from a second data sample from the FIR filter;
a first multiplier to multiply the first re-timed amplitude error and the second re-timed binary slope to generate the first phase error signal; and
a second multiplier to multiply the second re-timed amplitude error and the first re-timed binary slope to generate the second phase error signal.
8. The apparatus of claim 7 wherein the first phase error circuit comprises:
a re-timer to adjust the first data sample to a sample y(n);
a slicer coupled to the re-timer to generate a delayed ideal data sample delayed by P cycles y*(n\u2212P) from the sample y(n);
a delay to delay the sample y(n) to y(n\u2212P);
an amplitude subtractor coupled to the slicer and the delay to generate an amplitude error;
a re-timing and amplifying circuit to re-time and amplify the amplitude error to generate the first re-timed amplitude error;
a slope subtractor coupled to the delay and the re-timer to generate a difference between y(n\u2212P) and y(n);
a sign comparator coupled to the slope subtractor to generate a sign of the difference;
a synchronizer coupled to the sign comparator to generate the first re-timed binary slope synchronous with the first re-timed amplitude error.
9. The apparatus of claim 8 wherein the slicer comprises:
an analog-to-digital converter (ADC) to convert the sample y(n) to N levels according to a partial response polynomial;
N quantizers coupled to the ADC to quantize the N levels;
N synchronizers coupled to the N quantizers to delay the N quantized levels by P cycles; and
a digital-to-analog converter (DAC) to convert the delayed N quantized levels to the delayed ideal data sample y*(n\u2212P).
10. The apparatus of claim 7 wherein the second phase error circuit comprises:
a re-timer to adjust the second data sample to a sample y(n);
a slicer coupled to the re-timer to generate a delayed ideal data sample delayed by P cycles y*(n\u2212P) from the sample y(n);
a delay to delay the sample y(n) to y(n\u2212P);
an amplitude subtractor coupled to the slicer and the delay to generate an amplitude error;
a re-timing and amplifying circuit to re-time and amplify the amplitude error to generate the second re-timed amplitude error;
a slope subtractor coupled to the delay and the re-timer to generate a difference between y(n\u2212P) and y(n);
a sign comparator coupled to the slope subtractor to generate a sign of the difference;
a synchronizer coupled to the sign comparator to generate the second re-timed binary slope synchronous with the second re-timed amplitude error.
11. The apparatus of claim 10 wherein the slicer comprises:
an analog-to-digital converter (ADC) to convert the sample y(n) to N levels according to a partial response polynomial;
N quantizers coupled to the ADC to quantize the N levels;
N synchronizers coupled to the N quantizers to delay the N quantized levels by P cycles; and
a digital-to-analog converter (DAC) to convert the delayed N quantized levels to the delayed ideal data sample y*(n\u2212P).
12. A method comprising:
locking a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock using a frequency acquisition loop, the frequency acquisition loop generating first and second feedback clocks from the VCO clock;
generating a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock using a data lock phase loop, the driving signal controlling the multi-band VCO in a data phase lock mode; and
detecting a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock using a lock detect controller.
13. The method of claim 12 wherein locking the VCO clock comprises:
dividing the VCO clock to provide the first and second feedback clocks;
filtering a control signal using a loop filter, the filtered control signal controlling the multi-band VCO;
selecting the control signal from a common mode signal using a loop multiplexer, a frequency error signal, and the driving signal based on a multiplexer select code.
providing the frequency error signal based on the reference clock and the first feedback clock using a phase frequency detector (PFD) and a charge pump.
14. The method of claim 13 wherein detecting a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode comprises:
comparing the first feedback clock and the reference clock, the comparator generating a lock signal when a frequency difference of first feedback clock and the reference clock is less than a threshold value;
controlling the loop multiplexer and the multi-band VCO based on the lock signal and configuration bits; and
providing the configuration bits using a configuration register.
15. The method of claim 14 wherein controlling the loop multiplexer and the multi-band VCO comprises:
selecting a zone lock frequency band from a plurality of frequency bands of the multi-band VCO using a frequency coarse tuning circuit, the zone lock frequency band having a smallest frequency difference between the first feedback clock and the reference clock;
asserting the frequency lock condition using the selected zone lock frequency band; and
asserting the data lock condition.
16. The method of claim 14 wherein controlling the loop multiplexer and the multi-band VCO comprises generating the multiplexer select code to select the common mode signal, a frequency error signal, and the driving signal corresponding to the frequency coarse tuning circuit, the frequency fine tuning circuit, and the data phase lock control circuit, respectively.
17. The method of claim 12 wherein generating the driving signal corresponding to the phase error signal comprises:
generating the phase error signal using a minimum mean square error (MMSE) criteria in a decision-directed phase detector (DDPD), the DDPD receiving data samples from a finite impulse response (FIR) filter clocked by the second feedback clock to, the phase error signal including first and second phase error signals; and
generating a differential current from the phase error signal using a linear transconductor, the differential current corresponding to the driving signal that controls the multi-band VCO.
18. The method of claim 17 wherein generating the phase error signal comprises:
generating a first re-timed amplitude error and a first re-timed binary slope from a first data sample from the FIR filter;
generating a second re-timed amplitude error and a second re-timed binary slope from a second data sample from the FIR filter;
multiplying the first re-timed amplitude error and the second re-timed binary slope to generate the first phase error signal; and
multiplying the second re-timed amplitude error and the first re-timed binary slope to generate the second phase error signal.
19. The method of claim 18 wherein generating the first re-timed amplitude error and the first re-timed binary slope comprises:
adjusting the first data sample to a sample y(n);
generating a delayed ideal data sample delayed by P cycles y*(n\u2212P) from the sample y(n);
delaying the sample y(n) to y(n\u2212P);
generating an amplitude error;
re-timing and amplifying the amplitude error to generate the first re-timed amplitude error;
generating a difference between y(n\u2212P) and y(n);
generating a sign of the difference;
generating the first re-timed binary slope synchronous with the first re-timed amplitude error.
20. The method of claim 19 wherein generating the delayed ideal data sample comprises:
converting the sample y(n) to N levels according to a partial response polynomial;
quantizing the N levels;
delaying the N quantized levels by P cycles; and
converting the delayed N quantized levels to the delayed ideal data sample y*(n\u2212P).
21. The method of claim 18 wherein the second phase error circuit comprises:
adjusting the second data sample to a sample y(n);
generating a delayed ideal data sample delayed by P cycles y*(n\u2212P) from the sample y(n);
delaying the sample y(n) to y(n\u2212P);
generating an amplitude error;
re-timing and amplifying the amplitude error to generate the second re-timed amplitude error;
generating a difference between y(n\u2212P) and y(n);
generating a sign of the difference;
generating the second re-timed binary slope synchronous with the second re-timed amplitude error.
22. The method of claim 21 wherein generating the delayed ideal data sample comprises:
converting the sample y(n) to N levels according to a partial response polynomial;
quantizing the N levels;
delaying the N quantized levels by P cycles; and
converting the delayed N quantized levels to the delayed ideal data sample y*(n\u2212P).
23. A system comprising:
a variable gain amplifier (VGA) to amplify received optical data samples from a receiver optical channel;
a continuous time filter (CTF) coupled to the VGA to equalize the received optical data samples;
a finite impulse response (FIR) filter coupled to the CTF to generate interleaved partial response signal (PRS) samples;
a maximum likelihood (ML) sequence detector coupled to the FIR filter to recover the received samples; and
a timing recovery circuit (TRC) coupled to the FIR filter and the ML sequence detector to recover timing signal for the FIR filter and the sequence detector, the TRC comprising:
a frequency acquisition loop to lock a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock, the frequency acquisition loop generating first and second feedback clocks from the VCO clock, a data lock phase loop coupled to the frequency acquisition loop to generate a driving signal corresponding to a phase error signal from the interleaved PRS samples based on the second feedback clock, the driving signal controlling the multi-band VCO in a data phase lock mode, and a lock detect controller coupled to the frequency acquisition loop to detect a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock.
24. The system of claim 23 wherein the frequency acquisition loop comprises:
a divider to divide the VCO clock to provide the first and second feedback clocks;
a loop filter coupled to the multi-band VCO to filter a control signal, the filtered control signal controlling the multi-band VCO;
a loop multiplexer coupled to the loop filter to select the control signal from a common mode signal, a frequency error signal, and the driving signal based on a multiplexer select code.
a phase frequency detector (PFD) and a charge pump coupled to the loop multiplexer and the divider to provide the frequency error signal based on the reference clock and the first feedback clock.
25. The system of claim 24 wherein the lock detect controller comprises:
a comparator to compare the first feedback clock and the reference clock, the comparator generating a lock signal when a frequency difference of first feedback clock and the reference clock is less than a threshold value;
a control circuit coupled to the comparator to generate the multiplexer select code and band select code to the multi-band VCO based on the lock signal and configuration bits; and
a configuration register coupled to the control circuit to provide the configuration bits.
26. The system of claim 25 wherein the control circuit comprises:
a frequency coarse tuning circuit to select a zone lock frequency band from a plurality of frequency bands of the multi-band VCO, the zone lock frequency band having a smallest frequency difference between the first feedback clock and the reference clock;
a frequency fine tuning circuit coupled to the frequency coarse tuning circuit to assert or de-assert the frequency lock condition using the selected zone lock frequency band; and
a data phase lock control circuit coupled to the frequency fine tuning circuit to assert or de-assert the data lock condition.
27. The system of claim 25 wherein the control circuit generates the multiplexer select code to the loop multiplexer to select the common mode signal, a frequency error signal, and the driving signal corresponding to the frequency coarse tuning circuit, the frequency fine tuning circuit, and the data phase lock control circuit, respectively.
28. The system of claim 23 wherein the data lock phase loop comprises:
a decision-directed phase detector (DDPD) coupled to the FIR filter clocked by the second feedback clock to generate the phase error signal using a minimum mean square error (MMSE) criteria, the phase error signal including first and second phase error signals; and
a linear trans-conductor coupled to the DDPD to generate a differential current from the phase error signal, the differential current corresponding to the driving signal that controls the multi-band VCO.
29. The system of claim 28 wherein the DDPD comprises:
a first phase error circuit to generate a first re-timed amplitude error and a first re-timed binary slope from a first data sample from the FIR filter;
a second phase error circuit to generate a second re-timed amplitude error and a second re-timed binary slope from a second data sample from the FIR filter;
a first multiplier to multiply the first re-timed amplitude error and the second re-timed binary slope to generate the first phase error signal; and
a second multiplier to multiply the second re-timed amplitude error and the first re-timed binary slope to generate the second phase error signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An aqueous dispersion comprising (A) at least one thermoplastic resin; (B) at least one dispersing agent; and (C) water; wherein the dispersion has a pH of less than 12; wherein the thermoplastic resin comprises a copolymer of propylene with at least one comonomer selected from the group consisting of ethylene, a C4-C20 linear, branched or cyclic diene, and a compound represented by the formula H2C\u2550CHR wherein R is a C1-C20 linear, branched or cyclic alkyl group or a C6-C20 aryl group, wherein the copolymer of propylene is a propylene-rich alpha-olefin interpolymer comprising units derived from propylene and at least one comonomer selected from the group consisting of ethylene and C4 to C20 alpha-olefins, having a propylene content of greater than 65 mole percent a weight average molecular weight (Mw) of from about 15,000 to about 200,000, a weight average molecular weightnumber average molecular weight ratio (MwMn) of from about 1.5 to about 4, and a heat of fusion of from about 30 to about 80 Jg as determined by DSC.
2. The aqueous dispersion according to claim 1, wherein the propylene-rich alpha-olefin interpolymer is a propylene ethylene interpolymer.
3. The aqueous dispersion according to claim 2, wherein the propylene ethylene interpolymer has an ethylene content of about 5% to about 25% by weight.
4. The aqueous dispersion of claim 2, wherein the propylene ethylene interpolymer is a propylene-ethylene copolymer characterized as having 13C NMR peaks corresponding to a regio-error at about 14.6 and about 15.7 ppm, the peaks of about equal intensity.
5. An aqueous dispersion comprising (A) at least one thermoplastic resin; (B) at least one dispersing agent; and (C) water; wherein the dispersion has a pH of less than 12, and an average particle size of less than about 5 \u03bcm, and wherein the dispersing agent comprises less than about 4 percent by weight of the dispersion based on the weight of the thermoplastic resin, wherein the thermoplastic resin is a propylene-ethylene copolymer (a) characterized as having 13C NMR peaks corresponding to a regio-error at about 14.6 and about 15.7 ppm, the peaks of about equal intensity, and (b) wherein the ethylene is present in that copolymer in an amount of from about 5% to about 25% (by weight) and propylene is present in that copolymer in an amount of from about 95% to about 75% (by weight).
6. The aqueous dispersion of claim 2, wherein the propylene ethylene interpolymer is a propylene-ethylene copolymer made using a nonmetallocene, metal-centered, heteroaryl ligand catalyst.
7. The aqueous dispersion according to claim 2, wherein the propylene-rich interpolymer is characterized as having an isotactic triad (mm) measured by 13C-NMR of greater than about 0.85.
8. The aqueous dispersion of claim 2 wherein the interpolymer has a flexural modulus, measured in accordance with ASTM D-790-97, of less than about 50 kpsi.
9. The aqueous dispersion of claim 1 wherein the interpolymer has a melting point of less than about 140\xb0 C.
10. The aqueous dispersion of claim 2 wherein the interpolymer has a melting point of less than about 90\xb0 C.
11. The aqueous dispersion of claim 2 wherein the interpolymer has a heat of fusion of less than about 80 Jg.
12. The aqueous dispersion of claim 2, wherein the propylene-rich interpolymer is a propylene-ethylene copolymer characterized as having 13C NMR peaks corresponding to a regio-error at about 14.6 and about 15.7 ppm, the peaks of about equal intensity.
13. The aqueous dispersion of claim 3, wherein the propylene ethylene interpolymer is a propylene-ethylene copolymer characterized as having 13C NMR peaks corresponding to a regio-error at about 14.6 and about 15.7 ppm, the peaks of about equal intensity.
14. The aqueous dispersion of claim 3, wherein the propylene ethylene interpolymer is a propylene-ethylene copolymer made using a nonmetallocene, metal-centered, heteroaryl ligand catalyst.
15. An aqueous dispersion comprising (A) at least one thermoplastic resin; (B) at least one dispersing agent; and (C) water; wherein the dispersion has a pH of less than 12; wherein the thermoplastic resin comprises a copolymer of propylene with at least one comonomer selected from the group consisting of ethylene, a C4-C20 linear, branched or cyclic diene, and a compound represented by the formula H2C\u2550CHR wherein R is a C1-C20 linear, branched or cyclic alkyl group or a C6-C20 aryl group, wherein the copolymer of propylene is a propylene-rich alpha-olefin interpolymer comprising 5 to 25% by weight of ethylene content and 95 to 75% by weight of propylene content, the copolymer having:
(a) a melting point of less than 90C;
(b) a relationship of elasticity to 500% tensile modulus such that the elasticity is less than or equal to 0.935M+12, where elasticity is in percent and M is the 500% tensile modulus in MPa; and
(c) a relationship of flexural modulus to 500% tensile modulus such that flexural modulus is less than or equal to 4.2e0.27M+50, where flexural modulus is in MPa and M is the 500% tensile modulus in MPa.
16. The aqueous dispersion of claim 15, wherein the propylene ethylene interpolymer is a propylene-ethylene copolymer made using a nonmetallocene, metal-centered, heteroaryl ligand catalyst.
17. The aqueous dispersion according to claim 15, wherein the propylene-rich interpolymer is characterized as having an isotactic triad (mm) measured by 13C-NMR of greater than about 0.85.
18. The aqueous dispersion of claim 15, wherein the interpolymer has a flexural modulus, measured in accordance with ASTM D-790-97, of less than about 50 kpsi.
19. The aqueous dispersion of claim 15, wherein the interpolymer has a heat of fusion of less than about 80 Jg.
20. The aqueous dispersion of claim 1, wherein the dispersion has a pH ranging from about 7 to 11.
21. The aqueous dispersion of claim 15, wherein the dispersion has a pH ranging from about 7 to 11.