1. A semiconductor memory device comprising:
a semiconductor substrate having a first type conductivity;
a first buried layer formed in the semiconductor substrate and having a second type conductivity opposite to the first type conductivity;
a first well formed on the first buried layer and having the first type conductivity;
a second well formed in the first well over a first surface portion of the first buried layer and having the second type conductivity;
a second buried layer formed in the first well and on a second surface portion of the first buried layer and having the first type conductivity; and
a third well formed in the first well and on the second buried layer and having the second type conductivity.
2. The semiconductor memory device of claim 1, wherein the second well is formed on the first surface portion and electrically connected to the first buried layer.
3. The semiconductor memory device of claim 2, wherein the third well is electrically isolated from the first buried layer.
4. The semiconductor memory device of claim 2, wherein the first type conductivity corresponds to a P-type conductivity and the second type conductivity corresponds to an N-type conductivity.
5. The semiconductor memory device of claim 2, further comprising a first PMOS transistor formed in the second well and included in a sub-wordline driving circuit, and a second PMOS transistor formed in the third well and included in a sense amplifier.
6. The semiconductor memory device of claim 2, further comprising a first PMOS transistor formed in the third well and included in a sub-wordline driving circuit, and a second PMOS transistor formed in the second well and included in a sense amplifier.
7. The semiconductor memory device of claim 1, further comprising
a third buried layer formed in the first well interposed between the second well and the first surface portion of the first buried layer and having the first type conductivity.
8. The semiconductor memory device of claim 7, wherein the third well is electrically isolated from the first buried layer.
9. The semiconductor memory device of claim 7, wherein the first type conductivity corresponds to a P-type and the second type conductivity corresponds to an N-type.
10. The semiconductor memory device of claim 7, further comprising=a first PMOS transistor formed in the second well and included in a sub-wordline driving circuit, and a second PMOS transistor formed in the third well and included in a sense amplifier.
11. The semiconductor memory device of claim 7, further comprising a first PMOS transistor formed in the third well and included in a sub-wordline driving circuit, and a second PMOS transistor formed in the second well and included in a sense amplifier.
12. A method of manufacturing a semiconductor memory device comprising:
forming a first buried layer of a first type conductivity in a semiconductor substrate;
forming a first well of a second type conductivity opposite to the first type conductivity on the first buried layer;
forming a second well of the first type conductivity in the first well over a first surface portion of the first buried layer;
forming a second buried layer in the first well and on a second surface portion of the first buried layer; and
forming a third well of the first type conductivity in the first well and on the second buried layer.
13. The method of claim 12, wherein the second well is formed on the first surface portion and electrically connected to the first buried layer.
14. The method of claim 12, wherein the third well is formed by using a same mask as used to form the second buried layer.
15. The method of claim 12, further comprising forming a third buried layer in the first well interposed between the second well and the first surface portion of the first buried layer, the second buried layer and the third buried layer being isolated from each other.
16. The method of claim 15, wherein the second well and the third well are formed by using a same mask as used to form the second buried layer and the third buried layer.
17. A method of driving a semiconductor memory device including a semiconductor substrate having a first type conductivity, a first buried layer formed in the semiconductor substrate and having a second type conductivity opposite to the first type conductivity, a first well formed on the first buried layer and having the first type conductivity, a second well formed in the first well over a first surface portion of the first buried layer and having the second type conductivity, a second buried layer formed in the first well and on a second surface portion of the first buried layer and having the first type conductivity, and a third well formed in the first well and on the second buried layer and having the second type conductivity, the method comprising:
biasing the first buried layer with a first supply voltage;
biasing the first well with a second supply voltage that is lower than a ground voltage;
biasing the second well with the first supply voltage; and
biasing the third well with a third supply voltage.
18. The method of claim 17, wherein the third supply voltage is lower than the first supply voltage.
19. The method of claim 18, wherein the second supply voltage is a back bias voltage used in the semiconductor memory device.
20. The method of claim 18, wherein the first supply voltage is a boosted voltage used in a sub-wordline driving circuit of the semiconductor memory device and the third supply voltage is a supply voltage used in a sense amplifier of the semiconductor memory device.
21. The semiconductor memory device of claim 17, wherein the third supply voltage is higher than the first supply voltage.
22. The semiconductor memory device of claim 21, wherein the third supply voltage is a boosted voltage used in a sub-wordline driving circuit of the semiconductor memory device and the second supply voltage is a supply voltage used in a sense amplifier of the semiconductor memory device.
23. A method of biasing a semiconductor memory device including a semiconductor substrate having a first type conductivity, a first buried layer formed in the semiconductor substrate and having a second type conductivity opposite to the first type conductivity, a first well formed on the first buried layer and having the first type conductivity, a second well formed in the first well over a first surface portion of the first buried layer and having the second type conductivity, a second buried layer formed in the first well on a second surface portion of the first buried layer and having the first type conductivity; and a third well formed in the first well and interposed between the second well and the first surface portion of the first buried layer and having the second type conductivity, the method comprising:
biasing the first buried layer with a first supply voltage;
biasing the first well with a second supply voltage that is lower than a ground voltage;
biasing one of the second well and third well with the first supply voltage; and
biasing the other one of the second well and third well with a third supply voltage lower than the first supply voltage.
24. The method of claim 23, wherein the second supply voltage is a back bias voltage used in the semiconductor memory device.
25. The method of claim 23, wherein the first supply voltage is a boosted voltage used in a sub-wordline driving circuit of the semiconductor memory device and the third supply voltage is a supply voltage used in a sense amplifier of the semiconductor memory device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A degassing apparatus for use in association with a polymerisation reactor, the apparatus comprising:
a) a flash tank into which slurry from the reactor may be discharged and within which monomer(s) andor dilluent in the slurry may vaporise to form gas; and
b) a filter unit for removing suspended particles from the gas; wherein
c) the filter unit is directly connected to the flash tank without an intervening cyclone or the like.
2. A degassing apparatus as claimed in claim 1 wherein there is provided a plurality of filter units directly connected to the flash tank.
3. A degassing apparatus as claimed in claim 2, wherein valve apparatus is provided such that one of the filter units may be isolated for cleaning, removal or replacement whilst other filter(s) remain in operation.
4. A degassing apparatus as claimed in any preceding claim wherein the filter unit(s) isare mounted at an upper part of the flash tank and isare arranged such that particles thereby removed from the gas may fall into the flash tank.
5. A degassing apparatus for use in association with a polymerisation reactor, the apparatus comprising:
a) a flash tank into which slurry from the reactor may be discharged and within which monomer(s) andor dilluent in the slurry may vaporise to form gas; and
b) a filter unit for removing suspended particles from the gas; wherein the filter unit is mounted at an upper part of the flash tank and isare arranged such that particles thereby removed from the gas may fall into the flash tank.
6. A degassing apparatus as claimed in any preceding claim wherein the filter unit(s) are formed integrally with the flash tank.
7. A degassing apparatus for use in association with a polymerisation reactor, the apparatus comprising:
a) a flash tank into which slurry from the reactor may be discharged and within which monomer(s) andor dilluent in the slurry may vaporise to form gas; and
b) a plurality of filter units for removing suspended particles from the gas;
c) whereby the filter units are arranged such that one of the filter units may be isolated for cleaning, removal or replacement whilst other filter(s) remain in operation.
8. A degassing apparatus as claimed in any preceding claim wherein the filter units comprise bag filters.
9. A degassing apparatus as claimed in any preceding claim wherein the filter units comprise sintered metal filters.
10. A degassing apparatus as claimed in any preceding claim, further comprising a compressor for compressing the gas and a guard filter to protect the compressor from any particles not removed by the filter unit(s).
11. A degassing apparatus as claimed in any preceding claim further comprising a dryer for drying solid matter separated from the vaporised gas in the flash tank and for receiving solid matter from the filter unit(s).
12. A method of degassing a slurry from a polymerisation reactor comprising supplying the slurry to the apparatus of any preceding claim, allowing the apparatus to degas the slurry and thereby separating monomer gas andor dilluent from solid matter.
13. A method of producing a polymer whereby monomer, catalyst and other reactant(s) are supplied to a polymerisation reactor and the resultant slurry is supplied to a degassing apparatus as claimed in any of claims 1 to 11 whereby the polymer is separated from monomer gas.