What is claimed is:
1. A data communication method comprising the steps of:
encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side;
generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side;
recognizing transition in the signal of said M bits received via said transmission line and detecting the reception data of said M bits corresponding to said transmission clock on a reception side; and
decoding said M-bit reception data to said N-bit data on said reception side.
2. The data communication method according to claim 1,
wherein said transmission data is encoded so that at least one bit out of the M bits has one of binary logic values, and
wherein the level of the transmission data having the one of the logic values in said M-bit transmission data in said transmission signal is shifted synchronously with the transmission clock, and the transmission data having the other logic value is maintained at the same level.
3. The data communication method according to claim 2, wherein in said transmission data, two or larger bits of the same value out of said M bits have said one of logic values.
4. The data communication method according to claim 2, wherein on said reception side, transition in said reception signal is detected, a timing signal is generated, and the M-bit reception data in said reception signal is detected by the timing signal.
5. The data communication method according to claim 2, further comprising the steps of:
over-sampling the reception signal synchronously with a timing signal having a frequency which is a plurality of times as high as said transmission clock and receiving a plurality of sets of reception data on said reception side; and
detecting one accurate reception data from said reception data on said reception side.
6. The data communication method according to claim 2, further comprising the steps of:
converting a plurality of pieces of transmission data to parallel data and encoding each of the plurality of pieces of transmission data to transmission data of said M bits on said transmission side;
generating said transmission signal as serial data and transmitting said transmission signal synchronously with a transmission clock of a cycle corresponding to time shorter than time required for encoding on said transmission side;
recognizing transition in a reception signal of said M bits received via said transmission line and detecting the reception data of said M bits corresponding to said transmission clock on said reception side; and
converting the detected serial data into a plurality of pieces of parallel data and decoding the parallel data to said N-bit data on said reception side.
7. The data communication method according to claim 1, wherein said transmission signal includes said N-bit data and a control signal used for data communication, and transition takes place in signals of the same number which is two or larger in said N-bit data, including said control signal.
8. The data communication method according to claim 7, wherein said control signal includes a signal indicative of absence of data to be transmitted.
9. A data communication device comprising:
a transmission-side device including an encoder for encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger), and a transmission circuit for outputting a transmission signal in which transition takes place in at least one level of any of said transmission data synchronously with a transmission clock;
a transmission line to which the transmission signal of said transmission circuit is transmitted; and
a reception-side device including a reception circuit for recognizing transition in a reception signal of said M bits received via said transmission line and detecting the reception data of said M bits corresponding to said transmission clock and a decoder for decoding said reception data to said N-bit data.
10. The data communication device according to claim 9,
wherein said transmission-side device includes a signal processing circuit for generating said N-bit data, and
wherein said reception-side device includes a signal processing circuit for processing said N-bit data.
11. The data communication device according to claim 10, wherein said transmission-side device is formed on a single semiconductor chip.
12. The data communication device according to claim 10, wherein said reception-side device is formed on a single semiconductor chip.
13. The data communication device according to claim 10,
wherein the signal processing circuit of said transmission-side device is formed on a first semiconductor ship, said encoder and said transmission circuit are formed on a second semiconductor chip, and the first and second semiconductor chips are integrally sealed to form an apparently single semiconductor integrated circuit device, and
wherein the signal processing circuit of said reception-side device is formed on a third semiconductor chip, said reception circuit and said decoder are formed on a fourth semiconductor chip, and the third and fourth semiconductor chips are integrally sealed to form an apparently single semiconductor integrated circuit device.
14. The data communication device according to claim 10,
wherein said transmission-side device is constructed by a single semiconductor integrated circuit device,
wherein said reception-side device is constructed by a single semiconductor integrated circuit device, and
wherein said transmission line is wiring means formed on a mounting board on which the semiconductor integrated circuit devices constructing said transmission-side device and said reception-side device are mounted.
15. The data communication device according to claim 9,
wherein said encoder generates transmission data in which at least one bit out of M bits has one of binary logic values, and
wherein said transmission circuit generates a transmission signal which shifts the level of the data having said one of logic values out of said M-bit transmission data synchronously with a transmission clock and which makes the data having the other logic value maintained at the same level.
16. The data communication device according to claim 15, wherein said encoder generates transmission data in which bits of the same number which is two or larger out of said M bits have said one of logic values.
17. The data communication device according to claim 16, wherein said reception circuit detects the transition in said reception signal, generates a timing signal, and detects reception data of M bits by the timing signal.
18. The data communication device according to claim 16, wherein said reception circuit over-samples a reception signal by a timing signal having a frequency a plurality of times as high as that of said transmission clock, receives plural sets of reception data, and detects one accurate reception data from the reception data.
19. The data communication device according to claim 9,
wherein said transmission circuit converts the plurality of pieces of transmission data to parallel transmission data and encodes the parallel transmission data to said M-bit transmission data,
wherein said transmission circuit converts the transmission data to serial data, generates said transmission signal, and transmits said transmission signal to a transmission line synchronously with a transmission clock of a cycle corresponding to time shorter than time required for encoding,
wherein said reception circuit recognizes transition in a reception signal of said M bits received via said transmission line and detects said M-bit reception data corresponding to said transmission clock, and
wherein said decoder converts the detected serial data to a plurality of pieces of parallel data, and decodes the parallel data to said N-bit data.
20. The data communication device according to claim 9,
wherein said encoder generates transmission data of M bits including said N-bit data and a control signal used for data communication, and
wherein said transmission circuit generates transmission signals in which transition occurs in signals of the same number which is two or larger including said control signal.
21. The data communication device according to claim 20, wherein said control signal includes a signal indicative of absence of data to be transmitted.
22. The data communication device according to claim 16, in which said reception circuit comprises:
first MOSFETs connected in parallel for receiving a reception signal of M bits and each having an equivalent conductance characteristic; and
second MOSFETs of M pieces connected in parallel, in which (M1) MOSFETs have conductance equivalent to that of said first MOSFETs, and one MOSFET has a conductance which is the half of the conductance,
wherein a voltage corresponding to one of levels of said reception signal is supplied to gates of MOSFETs of the number corresponding to the number of bits having said one of logic values, which include the MOSFET having the half conductance, and a voltage corresponding to the other level of the reception signal is supplied to the gates of the remaining MOSFETs, and
wherein a circuit is included which detecta a difference between a current flowing in said first MOSFETs and a current flowing in said second MOSFETs and generates a detection signal indicative of validityinvalidity of the reception signal.
23. A semiconductor device comprising:
a first circuit for converting a first signal of N bits (N being 2 or larger) into a second signal of M bits (M being 3 or larger); and
a second circuit for receiving said second signal and outputting a third signal of said M bits,
wherein M is larger than N,
wherein said third signal is a signal in which transition takes place in level of a predetermined number of signals out of said third signals synchronously with a clock signal, and
wherein said third signal is output to the outside of said semiconductor device.
24. The semiconductor device according to claim 23,
wherein said third signal is input to a semiconductor device on the outside of said semiconductor device, and
wherein said semiconductor device on the outside includes a third circuit for recognizing transition in level of said third signal of said M bits on the basis of the clock signal and outputting a fourth signal of said M bits, and a fourth circuit for converting said fourth signal to a fifth signal of said N bits.
25. A semiconductor device comprising:
a first circuit for recognizing transition in level of a first signal of M bits (M being 3 or larger) on the basis of a clock signal and outputting a second signal of the M bits; and
a second circuit for receiving said second signal to a third signal of N bits (N being 2 or larger),
wherein M is larger than N,
wherein said first signal is a signal in which transition takes place in level of a predetermined number of signals out of said first signals synchronously with said clock signal, and
wherein said first signal is input from the outside of said semiconductor device.
26. The semiconductor device according to claim 25,
wherein said first signal is output from a semiconductor device on the outside of said semiconductor device, and
wherein said semiconductor device on the outside includes a third circuit for converting a fourth signal of said N bits to a fifth signal of said M bits, and a second circuit for receiving said fifth signal and outputting said first signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer-implemented method performed by a user equipment (UE), comprising:
generating, with a first chipset, a first set of geo-fence rules and a second set of geo-fence rules, which are a simplified subset of the first set of geo-fence rules;
transmitting the second set of geo-fence rules to a second chipset;
powering down the first chipset;
detecting if at least one of the second set of geo-fence rules has been broken; and
if at least one least one of the second set of geo-fence rules is broken, powering up the first chipset to determine if the at least one broken second rule is indicative of breaking at least one rule of the first set of geo-fence rules.
2. The computer-implemented method according to claim 1, further comprising, if at least one of the second set of geo-fence rules is broken and not indicative of breaking at least one of the first set of geo-fence rules, generating, with the first chipset, another second set of geo-fence rules which are a simplified subset of the first set of geo-fence rules, and transmitting the another second set of geo-fence rules to the second chipset.
3. The computer-implemented method according to claim 1, further comprising, if at least one of the second set of geo-fence rules is broken and indicative of breaking at least one of the first set of geo-fence rules, switching the second chipset to a continuous update mode, and monitoring, with the first chipset, a geo-fence area to the determine if the UE moves outside of the geo-fence area, and upon the UE moving outside of the geo-fence area, generating another second set of geo-fence rules.
4. The computer-implemented method according to claim 1, wherein the first chipset includes at least one first processor for controlling peripherals of the UE and at least one geo-fence module for generating the first set of geo-fence rules and the second set of geo-fence rules and controlling drivers of the UE, and the second chipset includes at least one low power clock and at least one second processor including at least one navigation ranging module, the at least one second processor programmed to detect if at least one of the second set of geo-fence rules has been broken.
5. The computer-implemented method according to claim 4, wherein powering down the first chipset comprises powering down the at least one geo-fence module.
6. The computer-implemented method according to claim 4, wherein powering down the first chipset comprises powering down the at least one geo-fence module and the at least one first processor of the first chipset.
7. The computer-implemented method according to claim 6, wherein powering down the first chipset further comprises powering down at least one clock of the second chipset, other than the at least one low power clock.
8. The computer-implemented method according to claim 4, further comprising:
determining, by the second chipset, if the second set of geo-fence rules should be redefined to include a long-term power down duration of the first chipset if the UE is a predetermined distance away from breaking the first set of geo-fence rules;
powering down the first chipset for the long-term power down duration; and
powering up the at least one low power clock of the second chipset for the long-term power down duration.
9. The computer-implemented method according to claim 1, wherein the second set of geo-fence rules is based on one of a convex hull configuration, a circle configuration, and a polygon configuration.
10. A user equipment (UE) comprising:
at least two chipsets; and
memory coupled to the at least two chipsets and configured to store instructions, which, when executed by the at least two chipsets, causes the at least two chipsets to perform operations comprising:
generating, with a first chipset, a first set of geo-fence rules and a second set of geo-fence rules, which are a simplified subset of the first set of geo-fence rules;
transmitting the second set of geo-fence rules to a second chipset;
powering down the first chipset;
detecting if at least one of the second set of geo-fence rules has been broken; and
if at least one least one of the second set of geo-fence rules is broken, powering up the first chipset to determine if the at least one broken second rule is indicative of breaking at least one rule of the first set of geo-fence rules.
11. The UE according to claim 10, wherein the at least two chipsets are programmed to perform operations further comprising, if at least one of the second set of geo-fence rules is broken and not indicative of breaking at least one of the first set of geo-fence rules, generating, with the first chipset, another second set of geo-fence rules which are a simplified subset of the first set of geo-fence rules, and transmitting the another second set of geo-fence rules to the second chipset.
12. The UE according to claim 10, wherein the at least two chipsets are programmed to perform operations further comprising, if at least one of the second set of geo-fence rules is broken and indicative of breaking at least one of the first set of geo-fence rules, switching the second chipset to a continuous update mode and monitoring, with the first chipset, a geo-fence area to the determine if the UE moves outside of the geo-fence area, and upon the UE moves outside of the geo-fence area, generating another second set of geo-fence rules.
13. The UE according to claim 10, wherein the first chipset includes at least one first processor for controlling peripherals of the UE and at least one geo-fence module for generating the first set of geo-fence rules and the second set of geo-fence rules and controlling drivers of the UE, and the second chipset includes at least one low power clock and at least one second processor including at least one navigation ranging module, the at least one second processor programmed to detect if at least one of the second set of geo-fence rules has been broken.
14. The UE according to claim 13, wherein powering down the first chipset comprises powering down the at least one geo-fence module.
15. The UE according to claim 13, wherein powering down the first chipset comprises powering down the at least one geo-fence module and the at least one first processor of the first chipset.
16. The UE according to claim 15, wherein powering down the first chipset further comprises powering down at least one clock of the second chipset, other than the at least one low power clock.
17. The UE according to claim 13, wherein the at least two chipsets are programmed to perform operations further comprising:
determining, by the second chipset, if the second set of geo-fence rules should be redefined to include a long-term power down duration of the first chipset if the UE is a predetermined distance away from breaking the first set of geo-fence rules;
powering down the first chipset for the long-term power down duration; and
powering up the at least one low power clock of the second chipset for the long-term power down duration.
18. The UE according to claim 10, wherein the second set of geo-fence rules is based on one of a convex hull configuration, a circle configuration, and a polygon configuration.
19. A user equipment (UE) comprising:
at least two chipsets; and
memory coupled to the at least two chipsets and configured to store instructions, which, when executed by the at least two chipsets, causes the at least two chipsets to perform operations comprising:
generating, with a first chipset, a first geo-fence area of the UE;
powering down the first chipset;
determining, by a second chipset programmed with navigational capabilities, if the UE moves outside of the first geo-fence area;
if the UE moves outside of the first geo-fence area, powering up the first chipset to determine if the UE has moved within another geo-fence area;
if it is determined that the UE has not moved within another geo-fence area, generating, with the first chipset, a second geo-fence area and transmitting the second geo-fence area to the second chipset; and
if it is determined that the UE has moved within another geo-fence area, switching the second chipset to a continuous update mode, and monitoring, with the first chipset, the another geo-fence area to the determine if the UE moves outside of the another geo-fence area, and upon the UE moving outside of the another geo-fence area, generating the second geo-fence area and transmitting the second geo-fence area to the second chipset.
20. A user equipment (UE) comprising:
at least two chipsets; and
memory coupled to the at least two chipsets and configured to store instructions, which, when executed by the at least two chipsets, causes the at least two chipsets to perform operations comprising:
generating, with a first chipset, a first geo-fence area of the UE and a time duration for which it would take the UE to move outside the first geo-fence area;
powering down the first chipset for the time duration;
transmitting the time duration to a second chipset;
if, upon expiration of the time duration, it is determined that the UE has not moved within another geo-fence area, generating, with the first chipset, a second geo-fence area and a second time duration for which it would take the UE to move outside the second geo-fence area, and transmitting the second time duration to the second chipset; and
if, upon expiration of the time duration, it is determined that the UE has moved within another geo-fence area, switching the second chipset to a continuous update mode, and monitoring, with the first chipset, the another geo-fence area to the determine if the UE moves outside of the another geo-fence area, and upon the UE moving outside of the another geo-fence area, generating the second geo-fence area and the second time duration, and transmitting the second time duration to the second chipset.