1. A sample processing apparatus, comprising:
a first mechanism unit having a first operation range of movement and that carries out a first process on a container with a sample, the first operation range comprising an overlap region and a non-overlap region;
a second mechanism unit having a second operation range of movement and that carries out a second process on the container after completion of the first process, the second operation range comprising the overlap region but not the non-overlap region;
a detector that senses operation of the first mechanism unit; and
a controller that causes the first mechanism unit to stop the first process and retreat from the overlap region and that causes the second mechanism unit to continue the second process upon detection of abnormality in the first mechanism unit by the detector.
2. The sample processing apparatus according to claim 1, wherein
the first mechanism unit includes a first reagent dispenser, and
the second mechanism unit includes a container transfer that moves the container after operation of the first reagent dispenser.
3. The sample processing apparatus according to claim 2, wherein the first reagent dispenser dispenses reagent into the container in the overlap region.
4. The sample processing apparatus according to claim 2, further comprising:
a reactor that holds the container after the dispensing process and allows reaction between the sample and the reagent in the container; and
a separator that separates unreacted components of the sample and the reagent from the container, wherein
the container transfer transfers the container to the reactor after the dispensing process and transfers the container from the reaction part to the separator, via a path that passes through the overlap region, after the reaction.
5. The sample processing apparatus according to claim 4, further comprising a second reagent dispenser that dispenses a second reagent into the container, wherein
the container transfer transfers the container to the separator after dispensing of the second reagent and moves the container after the separation process to the overlap region, and then
the first reagent dispenser dispenses the reagent into the container transferred from the separation process part to the overlap region by the container transfer.
6. The sample processing apparatus according to claim 5, wherein the container transfer transfers the container to the reactor after operation of dispensing of the reagent by the second reagent dispenser and then after reaction to the separator through the overlap region.
7. The sample processing apparatus according to claim 2, wherein
the first mechanism unit includes a pipette that dispenses the reagent and an elevating mechanism that moves the pipette vertically,
the detector includes a collision detecting sensor that detects collision of the pipette, and
the controller determines collision abnormality of the pipette based on the detection result by the collision detecting sensor.
8. The sample processing apparatus according to claim 2, wherein
the first mechanism unit includes a pipette that dispenses the reagent and an elevating mechanism that moves the pipette vertically,
the operation detector includes a first base point sensor that detects an upper base point position of the pipette in the vertical direction, and
the controller detects an abnormality related to return of the first mechanism unit to the upper base point position, from output of the first base point sensor.
9. The sample processing apparatus according to claim 2, wherein
the first mechanism unit includes a motor that moves the first mechanism unit between the overlap region and the non-overlap region,
the detector includes an encoder that detects a rotational position of the motor, and
the controller detects an abnormality related to movement of the first mechanism unit between the overlap region and the non-overlap region, based on a result of detection with the encoder.
10. The sample processing apparatus according to claim 1, wherein
the detector includes a second base point sensor that detects a horizontal base point position of the first mechanism unit in a horizontal direction in the non-overlap region, and
upon detection via the second base point sensor of the abnormality in the first mechanism unit, the controller causes the first mechanism unit to retreat to the horizontal base point position based on the detection result by the second base point sensor.
11. The sample processing apparatus according to claim 10, wherein
the first mechanism unit is a first reagent dispenser that dispenses a reagent into the container, and
the sample processing apparatus further comprises a cleaner at the base point position that cleans the first mechanism unit after dispensing the reagent.
12. The sample processing apparatus according to claim 1, wherein the controller stops both the first mechanism unit and the second mechanism unit, upon detection of an abnormality in the first mechanism unit during a retreating operation of the first mechanism unit to the non-overlap region.
13. The sample processing apparatus according to claim 1, further comprising
a mechanism that transfers the container, and
a mechanism that transfers the container after transfer of the container by the first mechanism.
14. The sample processing apparatus according to claim 1, further comprising a measuring part that measures the sample after the second process by the second mechanism unit, wherein
the first mechanism unit and the second mechanism unit are arranged at a first level, and
the measuring part is arranged at a second level below the first level.
15. The sample processing apparatus according to claim 4, wherein
the reactor heats the sample and the reagent for a predetermined time to a predetermined temperature.
16. The sample processing apparatus according to claim 2, wherein the detector comprises a sensor that detects discharge of the reagent by the first reagent dispenser, and thereby allows the controller to detect an abnormality in the first reagent dispenser from detection of discharge of the reagent by the first reagent dispenser.
17. The sample processing apparatus according to claim 14, further comprising an inter-level transporter that transports the container from the first level to the second level.
18. A sample processing method, comprising steps of:
a first movement of a container having a sample, within a first operation range that includes an overlap region and a non-overlap region by a first mechanism unit; then
a second movement of the container within a second operation range including the overlap region and not overlapping the non-overlap region by a second mechanism unit;
detecting operation of the first mechanism unit;
controlling the first mechanism unit to stop the movement by the first mechanism unit and retreat from the overlap region; and
controlling the second mechanism unit to continue the first movement upon detection of abnormality in the first mechanism unit based on a result of the detecting step.
19. The sample processing method according to claim 18, further comprising steps of:
dispensing a reagent into the container; and
moving the container after the dispensing step.
20. The sample processing method according to claim 19, wherein
the dispensing step is performed within the overlap region.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory cell, comprising:
a ferroelectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the well region and the substrate;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first sourcedrain region having the first conductivity type formed in the well region and coupled to a program line;
a second sourcedrain region having the first conductivity type formed in the well region;
a channel region having the first conductivity type formed in the well region and interposed between the first and second sourcedrain regions; and
a diode interposed between the second sourcedrain region and a bit line.
2. The memory cell of claim 1, wherein the ferroelectric layer is formed overlying and adjoining the well region having the first conductivity type and wherein the diode is a well region having a second conductivity type formed in the second sourcedrain region.
3. The memory cell of claim 1, wherein the ferroelectric layer is adjoining the well region.
4. The memory cell of claim 1, wherein the ferroelectric layer comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure.
5. The memory cell of claim 1, further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer; and
a floating gate interposed between the gate dielectric layer and the ferroelectric layer.
6. The memory cell of claim 5, wherein the floating gate comprises a conductive material.
7. The memory cell of claim 6, wherein the conductive material includes at least one material selected from the group consisting of conductively-doped polysilicon, metal silicides, metals and metal alloys.
8. The memory cell of claim 7, wherein the floating gate comprises a metal layer overlying a conductively-doped polysilicon layer.
9. The memory cell of claim 1, further comprising:
a gate dielectric layer interposed between the channel region and the ferroelectric layer;
wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer.
10. A memory cell, comprising:
a ferroelectric layer formed overlying and adjoining a well region having a first conductivity type, wherein the well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the well region and the substrate;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first sourcedrain region having the first conductivity type formed in the well region and coupled to a program line;
a second sourcedrain region having the first conductivity type formed in the well region;
a channel region having the first conductivity type formed in the well region and interposed between the first and second sourcedrain regions; and
a diode interposed between the second sourcedrain region and a bit line.
11. A memory cell, comprising:
a gate dielectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the well region and the substrate;
a ferroelectric layer formed overlying the gate dielectric layer;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first sourcedrain region having the first conductivity type formed in the well region and coupled to a program line;
a second sourcedrain region having the first conductivity type formed in the well region;
a channel region having the first conductivity type formed in the well region and interposed between the first and second sourcedrain regions; and
a diode interposed between the second sourcedrain region and a bit line.
12. The memory cell of claim 11, wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer.
13. A memory cell, comprising:
a gate dielectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the well region and the substrate;
a conductive floating gate formed overlying the gate dielectric layer;
a ferroelectric layer formed overlying the conductive floating gate;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first sourcedrain region having the first conductivity type formed in the well region and coupled to a program line;
a second sourcedrain region having the first conductivity type formed in the well region;
a channel region having the first conductivity type formed in the well region and interposed between the first and second sourcedrain regions; and
a diode interposed between the second sourcedrain region and a bit line.
14. The memory cell of claim 13, wherein the ferroelectric layer is overlying and adjoining the conductive floating gate.
15. A memory cell, comprising:
a ferroelectric layer formed overlying a well region having a first conductivity type, wherein the well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the well region and the substrate;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first sourcedrain region having the first conductivity type formed in the well region and coupled to a program line;
a second sourcedrain region having the first conductivity type formed in the well region;
a channel region having the first conductivity type formed in the well region and interposed between the first and second sourcedrain regions; and
a diode formed as a second well region of a second conductivity type in the second sourcedrain region and coupled to a bit line, wherein the second conductivity type is opposite the first conductivity type.
16. The memory cell of claim 15, wherein the ferroelectric layer comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure.
17. A memory cell, comprising:
a gate dielectric layer formed overlying and adjoining a well region having a first conductivity type, wherein the well region is formed in a substrate having a second conductivity type opposite the first conductivity type;
a conductive floating gate formed overlying the gate dielectric layer;
a ferroelectric layer formed overlying the conductive floating gate;
a control gate formed overlying the ferroelectric layer and coupled to a word line;
a first sourcedrain region having the first conductivity type formed in the well region and coupled to a program line;
a second sourcedrain region having the first conductivity type formed in the well region;
a channel region having the first conductivity type formed in the well region and interposed between the first and second sourcedrain regions; and
a diode formed as a second well region of a second conductivity type in the second sourcedrain region and coupled to a bit line, wherein the second conductivity type is opposite the first conductivity type.
18. The memory cell of claim 17, wherein the ferroelectric layer is formed overlying and adjoining the conductive floating gate.
19. The memory cell of claim 17, wherein the ferroelectric layer comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure.