1. A cyclic redundancy check (CRC) verification apparatus having constant delay, comprising:
a data buffer which stores an input data frame;
a control information buffer which stores control information on the data frame;
a CRC generation unit which performs CRC verification of the data frame;
an input control unit which receives an input control signal, generates a CRC enable signal, sends the CRC enable signal to the CRC generation unit, generates information on a write address which increases sequentially irrespective of the input of the data frame, sends the write address information to the data buffer and the control information buffer, and with storing an address in which the start part of the data frame is stored, if input of the data frame finishes, receives the CRC verification result from the CRC generation unit and stores the CRC verification result in the address in which the start part of the data frame is stored, and provides a read address synchronization signal that makes a read address follows with a predetermined offset after the write address; and
an output control unit which receives the read address synchronization signal, generates the read address which increases sequentially, sends the read address to the data buffer and the control information buffer, reads data stored in the data buffer, and outputs a different output control signal together with the data according to the CRC result,
wherein the CRC verification apparatus receives input frames at a constant rate irrespective of a received data frame while CRC verification is performed.
2. The apparatus of claim 1, wherein the control information includes information on the start of the data frame, end information, buffer enable information and CRC verification result information.
3. The apparatus of claim 1, further comprising:
a retiming unit which retimes data according to a command from the output control unit, by outputting data \u20180\u2019 when there is no input data frame, or by not latching data in the data buffer.
4. The apparatus of claim 1, wherein the predetermined offset is the same value as the maximum length of the data frame or a value exceeding the maximum length by a predetermined degree.
5. A CRC verification apparatus having constant delay, comprising:
a buffer which stores an input data frame and control information on a data frame;
a CRC generation unit which performs CRC verification of the data frame;
an input control unit which receives an input control signal, generates a CRC enable signal, sends the CRC enable signal to the CRC generation unit, generates information on a write address which increases sequentially irrespective of the input of the data frame, sends the write address information to the buffer, and with storing an address in which the start part of the data frame is stored, if input of the data frame finishes, receives the CRC verification result from the CRC generation unit and stores the CRC verification result in the address in which the start part of the data frame is stored, and provides a read address synchronization signal that makes a read address follows with a predetermined offset after the write address; and
an output control unit which receives the read address synchronization signal, generates the read address which increases sequentially, sends the read address information to the buffer, reads data stored in the buffer, and outputs a different output control signal together with the data according to the CRC result,
wherein the CRC verification apparatus receives input frames at a canstant rate irrespective of a received data frame while CRC verification is performed.
6. The apparatus of claim 5, wherein the predetermined offset is the same value as the maximum length of the data frame or a value exceeding the maximum length by a predetermined degree.
7. A CRC verification apparatus having constant delay, comprising:
an input control unit which stores the start address of an input data frame in a memory storing the input data frame, and stores a CRC verification result in the start address location; and
an output control unit which with a predetermined offset from the write address, reads the input data frames and if the CRC verification result is normal, output the read data frame,
wherein the CRC verification apparatus receives input frames at a constant rate irrespective of a received data frame while CRC verification is performed.
8. The apparatus of claim 7, wherein the predetermined constant time is the same value as the maximum length of the data frame or a value exceeding the maximum length by a predetermined degree.
9. A CRC verification method having constant delay, comprising:
receiving an input data frame;
storing the input data frame and recording the start address in which the data frame is stored;
performing CRC verification of the data frame;
receiving an input control signal, generating a CRC enable signal, generating write address which increases sequentially irrespective of the input of the data frame, and with storing an address in which the start part of the data frame is stored, if input of the data frame finishes, receiving the CRC verification result from the CRC generation unit and storing the CRC verification result in the address in which the start part of the data frame is stored, and providing a read address synchronization signal that makes the read address follow with a predetermined offset after the write address; and
receiving the read address synchronization signal, generating information on a read address which increases sequentially, reading the stored data frame according to this read address information, and according to the CRC result, outputting a different output control signal together with the output data,
wherein input frames are received at a constant rate irrespective of received data frames while the CRC verification is performed.
10. The method of claim 9, wherein the predetermined length is the same value as the maximum length of the data frame or a value exceeding the maximum length by a predetermined degree.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A heterojunction bipolar transistor comprising: a low-concentration n-type collector layer formed a semi-insulating substrate; a high-concentration p-type base layer formed on the collector layer; a low-concentration n-type emitter layer formed on the base layer; a base ohmic electrode which is made of a single layer or a plurality of layers and which is formed on a base protective layer that is a portion of the emitter layer; a high-concentration n-type emitter contact layer formed so as to cover regions of the emitter layer except the base protective layer; and an emitter ohmic electrode which is made of a single layer or a plurality of layers and which is formed on the emitter contact layer, further comprising:
a base-use alloyed reaction layer formed under the base ohmic electrode, and an emitter-use alloyed reaction layer formed under the emitter ohmic electrode, wherein
the base-use alloyed reaction layer extends through the base protective layer so as to reach the base layer and the emitter-use alloyed reaction layer is formed only within the emitter contact layer.
2. The heterojunction bipolar transistor according to claim 1, wherein
the base ohmic electrode and the emitter ohmic electrode are made of an identical material.
3. The heterojunction bipolar transistor according to claim 1, wherein
the emitter contact layer is composed of a first emitter contact layer and a second emitter contact layer formed on the first emitter contact layer;
carrier concentration of the second emitter contact layer is set so as to be higher than carrier concentration of the first emitter contact layer; and
the emitter-use alloyed reaction layer is formed only within the second emitter contact layer.
4. The heterojunction bipolar transistor according to claim 1, wherein
the collector layer and the base layer are formed of GaAs and the emitter layer and the base protective layer are formed of AlGaAs.
5. The heterojunction bipolar transistor according to claim 1, wherein the first emitter contact layer is formed of GaAs and the second emitter contact layer is formed of InGaAs.
6. The heterojunction bipolar transistor according to claim 1, wherein
the base ohmic electrode and the emitter ohmic electrode, or a lowermost layer of the base ohmic electrode and a lowermost layer of the emitter ohmic electrode are made of Pt; and
the base-use alloyed reaction layer and the emitter-use alloyed reaction layer contain Pt.
7. A method for manufacturing the heterojunction bipolar transistor as defined in claim 3, comprising the steps of:
stacking, on the base protective layer and the second emitter contact layer, an electrode material that makes the base ohmic electrode and the emitter ohmic electrode, or an electrode material Pt that makes a lowermost layer of the base ohmic electrode and a lowermost layer of the emitter ohmic electrode, so that a film thickness of the electrode material becomes thinner than a film thickness of the second emitter contact layer; and
subjecting the electrode material to a heat treatment to form the base ohmic electrode on the base protective layer and form the emitter ohmic electrode on the second emitter contact layer.
8. The method for manufacturing the heterojunction bipolar transistor according to claim 7, wherein
the film thickness of the second emitter contact layer is set to three or more times the film thickness of the electrode material Pt.
9. The method for manufacturing the heterojunction bipolar transistor according to claim 7, wherein
the film thickness of the electrode material is within a range defined by a following relational expression:
(film thickness of the base protective layer)<film thickness of the electrode material before heat treatment<(film thickness of the base protective layerfilm thickness of the base layer ).