1. A system for handling electronic information, comprising:
a rectangle module that detects write operations to on-screen data in a video memory, said rectangle module updating a primary transfer rectangle during a normal mode to include pixel data from said write operations;
a coordinates module that stores primary rectangle coordinates defining said primary transfer rectangle for performing a current transfer operation; and
controller logic that instructs said coordinates module to enter a pause mode before initiating said current transfer operation, said coordinates module retaining said primary rectangle coordinates during said pause mode, said coordinates module also storing secondary rectangle coordinates for a secondary transfer rectangle formed during said pause mode by continuing to detect said write operations, said controller logic instructing said coordinates module to resume said normal mode after said current transfer operation concludes, said coordinates module then responsively replacing said primary rectangle coordinates with said secondary rectangle coordinates for performing a subsequent transfer operation.
2. The system of claim 1 wherein said controller logic, said rectangle module, and said coordinates module are a part of a display controller that is implemented as an integrated circuit device that functions as a transparent interface between a central processing unit and a display of a host electronic device.
3. The system of claim 1 wherein said controller logic, said rectangle module, and said coordinates module are implemented in a display controller that coordinates image-data transfer operations for providing image data to a random-access-memory based liquid-crystal display of a portable electronic device.
4. The system of claim 3 wherein said portable electronic device is implemented as a cellular telephone that utilizes said display controller to conserve system resources and operating power by performing a partial transfer with said primary transfer rectangle during said image-data transfer operations.
5. The system of claim 1 wherein said controller logic instructs said coordinates module to enter said pause mode by setting a pause flag, said controller logic subsequently instructing said coordinates module to resume said normal mode after said current transfer operation concludes by resetting said pause flag.
6. The system of claim 1 wherein said coordinates module stores said secondary rectangle coordinates for said secondary transfer rectangle during said pause mode to prevent losing any of said pixel data that is written to said on-screen data of said video memory during said current transfer operation.
7. The system of claim 1 wherein said rectangle module updates a current primary transfer rectangle during said normal mode to produce an updated primary transfer rectangle whenever said pixel data from said write operations is located outside of said current primary transfer rectangle, said rectangle module also updating a current secondary transfer rectangle during both said normal mode and said pause mode to produce an updated secondary transfer rectangle whenever said pixel data from said write operations is located outside of said current secondary transfer rectangle.
8. The system of claim 1 wherein said primary transfer rectangle is defined by a rectangle notation:
(x1,y1),(x2,y2)
where said (x1, y1) are pixel coordinates of a top left pixel from said primary transfer rectangle, and where said (x2, y2) are bottom right coordinates of said primary transfer rectangle.
9. The system of claim 8 wherein said rectangle module detects that a new pixel (X, Y) has been written into said on-screen data, said rectangle module responsively performing four tests for updating said primary transfer rectangle, said rectangle module determining whether said X is less than said x1, and if so, then updating said x1 to equal said X, said rectangle module also determining whether said X is greater than said x2, and if so, then updating said x2 to equal said X, said rectangle module further determining whether said Y is less than said y1, and if so, then updating said y1 to equal said Y, said rectangle module finally determining whether said Y is greater than said y2, and if so, then updating said y2 to equal said Y.
10. The system of claim 1 wherein said coordinates module includes a primary latch for storing said primary rectangle coordinates, said coordinates module also including a secondary latch for storing said secondary rectangle coordinates.
11. The system of claim 10 wherein said rectangle module continually provides updated rectangle coordinates for updated transfer rectangles to said secondary latch which stores said updated rectangle coordinates as said secondary rectangle coordinates, said secondary latch also passing said secondary rectangle coordinates during said normal mode to said primary latch which stores said secondary rectangle coordinates as said primary rectangle coordinates, said primary latch retaining said primary rectangle coordinates during said pause mode, said secondary latch continuing to update said secondary rectangle coordinates during said pause mode, said primary latch again receiving and storing said secondary rectangle coordinates as primary rectangle coordinates only after said current transfer operation is completed and said normal mode is resumed.
12. The system of claim 1 wherein performing a partial transfer of only said current transfer rectangle conserves system resources and operating power for a host electronic device because said partial transfer operates on a reduced amount of image data when compared to transferring entire frames of said on-screen data from said video memory.
13. The system of claim 1 wherein a primary latch of said coordinates module updates and stores said primary rectangle coordinates when notified by said rectangle module regarding at least one of said write operations to said on-screen data.
14. The system of claim 13 wherein said controller logic initiates said current transfer operation in response to a transfer trigger event that alternately includes a transfer clock trigger that occurs after a pre-determined transfer interval has been exceeded, and a write-operation counter trigger that indicates that a total written pixel value has exceeded a pre-determined write-operation pixel threshold.
15. The system of claim 14 wherein said controller logic sets a pause flag to instruct said coordinates module to enter said pause mode in response to said transfer trigger event, said controller logic then coordinating said current transfer operation.
16. The system of claim 15 wherein said controller logic resets said pause flag when said current transfer operation is completed to resume said normal mode, said primary latch then receiving and storing said secondary rectangle coordinates as said primary rectangle coordinates for performing said subsequent transfer operation.
17. The system of claim 1 wherein a secondary latch in said coordinates module updates and stores said secondary rectangle coordinates when notified by said rectangle module regarding at least one of said write operations to said on-screen data.
18. The system of claim 17 wherein said controller logic sets a pause flag and initiates said current transfer operation in response to a transfer trigger event that alternately includes a transfer clock trigger after a pre-determined transfer interval has been exceeded, and write-operation counter trigger that indicates that a total written pixel value has exceeded a pre-determined write-operation pixel threshold.
19. The system of claim 18 wherein said controller logic resets said pause flag when said current transfer operation is completed to resume said normal mode.
20. The system of claim 19 wherein said secondary latch deletes a current version of said secondary rectangle coordinates when said pause flag is reset, and said primary latch then storing said secondary rectangle coordinates as said primary rectangle coordinates for performing said subsequent transfer operation.
21. A method for handling electronic information, comprising the steps of:
detecting write operations to on-screen data in a video memory by utilizing a rectangle module that updates a primary transfer rectangle during a normal mode to include pixel data from said write operations;
storing primary rectangle coordinates with a coordinates module, said primary rectangle coordinates defining said primary transfer rectangle for performing a current transfer operation;
instructing said coordinates module to enter a pause mode before initiating said current transfer operation by utilizing controller logic, said coordinates module retaining said primary rectangle coordinates during said pause mode, said coordinates module also storing secondary rectangle coordinates for a secondary transfer rectangle formed during said pause mode by continuing to detect said write operations; and
resuming said normal mode after said current transfer operation concludes, said coordinates module then responsively replacing said primary rectangle coordinates with said secondary rectangle coordinates for performing a subsequent transfer operation.
22. The method of claim 21 wherein said controller logic, said rectangle module, and said coordinates module are a part of a display controller that is implemented as an integrated circuit device that functions as a transparent interface between a central processing unit and a display of a host electronic device.
23. The method of claim 21 wherein said controller logic, said rectangle module, and said coordinates module are implemented in a display controller that coordinates image-data transfer operations for providing image data to a random-access-memory based liquid-crystal display of a portable electronic device.
24. The method of claim 23 wherein said portable electronic device is implemented as a cellular telephone that utilizes said display controller to conserve system resources and operating power by performing a partial transfer with said primary transfer rectangle during said image-data transfer operations.
25. The method of claim 21 wherein said controller logic instructs said coordinates module to enter said pause mode by setting a pause flag, said controller logic subsequently instructing said coordinates module to resume said normal mode after said current transfer operation concludes by resetting said pause flag.
26. The method of claim 21 wherein said coordinates module stores said secondary rectangle coordinates for said secondary transfer rectangle during said pause mode to prevent losing any of said pixel data that is written to said on-screen data of said video memory during said current transfer operation.
27. The method of claim 21 wherein said rectangle module updates a current primary transfer rectangle during said normal mode to produce an updated primary transfer rectangle whenever said pixel data from said write operations is located outside of said current primary transfer rectangle, said rectangle module also updating a current secondary transfer rectangle during both said normal mode and said pause mode to produce an updated secondary transfer rectangle whenever said pixel data from said write operations is located outside of said current secondary transfer rectangle.
28. The method of claim 21 wherein said primary transfer rectangle is defined by a rectangle notation:
(x1,y1),(x2,y2)
where said (x1, y1) are pixel coordinates of a top left pixel from said primary transfer rectangle, and where said (x2, y2) are bottom right coordinates of said primary transfer rectangle.
29. The method of claim 28 wherein said rectangle module detects that a new pixel (X, Y) has been written into said on-screen data, said rectangle module responsively performing four tests for updating said primary transfer rectangle, said rectangle module determining whether said X is less than said x1, and if so, then updating said x1 to equal said X, said rectangle module also determining whether said X is greater than said x2, and if so, then updating said x2 to equal said X, said rectangle module further determining whether said Y is less than said y1, and if so, then updating said y1 to equal said Y, said rectangle module finally determining whether said Y is greater than said y2, and if so, then updating said y2 to equal said Y.
30. The method of claim 21 wherein said coordinates module includes a primary latch for storing said primary rectangle coordinates, said coordinates module also including a secondary latch for storing said secondary rectangle coordinates.
31. The method of claim 30 wherein said rectangle module continually provides updated rectangle coordinates for updated transfer rectangles to said secondary latch which stores said updated rectangle coordinates as said secondary rectangle coordinates, said secondary latch also passing said secondary rectangle coordinates during said normal mode to said primary latch which stores said secondary rectangle coordinates as said primary rectangle coordinates, said primary latch retaining said primary rectangle coordinates during said pause mode, said secondary latch continuing to update said secondary rectangle coordinates during said pause mode, said primary latch again receiving and storing said secondary rectangle coordinates as primary rectangle coordinates only after said current transfer operation is completed and said normal mode is resumed.
32. The method of claim 21 wherein performing a partial transfer of only said current transfer rectangle conserves system resources and operating power for a host electronic device because said partial transfer operates on a reduced amount of image data when compared to transferring entire frames of said on-screen data from said video memory.
33. The method of claim 21 wherein a primary latch of said coordinates module updates and stores said primary rectangle coordinates when notified by said rectangle module regarding at least one of said write operations to said on-screen data.
34. The method of claim 33 wherein said controller logic initiates said current transfer operation in response to a transfer trigger event that alternately includes a transfer clock trigger that occurs after a pre-determined transfer interval has been exceeded, and write-operation counter trigger that indicates that a total written pixel value has exceeded a pre-determined write-operation pixel threshold.
35. The method of claim 34 wherein said controller logic sets a pause flag to instruct said coordinates module to enter said pause mode in response to said transfer trigger event, said controller logic then coordinating said current transfer operation.
36. The method of claim 35 wherein said controller logic resets said pause flag when said current transfer operation is completed to resume said normal mode, said primary latch then receiving and storing said secondary rectangle coordinates as said primary rectangle coordinates for performing said subsequent transfer operation.
37. The method of claim 21 wherein a secondary latch in said coordinates module updates and stores said secondary rectangle coordinates when notified by said rectangle module regarding at least one of said write operations to said on-screen data.
38. The method of claim 37 wherein said controller logic sets a pause flag and initiates said current transfer operation in response to a transfer trigger event that alternately includes a transfer clock trigger after a pre-determined transfer interval has been exceeded, and write-operation counter trigger that indicates that a total written pixel value has exceeded a pre-determined write-operation pixel threshold.
39. The method of claim 38 wherein said controller logic resets said pause flag when said current transfer operation is completed to resume said normal mode.
40. The method of claim 39 wherein said secondary latch deletes a current version of said secondary rectangle coordinates when said pause flag is reset, and said primary latch then storing said secondary rectangle coordinates as said primary rectangle coordinates for performing said subsequent transfer operation.
41. A system for handling electronic information, comprising:
means for detecting write operations to on-screen data in a video memory, said means for detecting then updating a primary transfer rectangle during a normal mode to include pixel data from said write operations;
means for storing primary rectangle coordinates that define said primary transfer rectangle for performing a current transfer operation;
means for entering a pause mode before initiating said current transfer operation:
means for retaining said primary rectangle coordinates during said pause mode, said means for retaining also storing secondary rectangle coordinates for a secondary transfer rectangle formed during said pause mode by continuing to detect said write operations; and
means for resuming said normal mode after said current transfer operation concludes, said means for retaining then responsively replacing said primary rectangle coordinates with said secondary rectangle coordinates for performing a subsequent transfer operation.
42. A system for handling electronic information, comprising:
a rectangle module that updates a primary transfer rectangle to include pixel data from write operations to a video memory; and
a coordinates module that stores primary rectangle coordinates defining said primary transfer rectangle for performing a current transfer operation, said coordinates module also storing secondary rectangle coordinates for a secondary transfer rectangle formed by continuing to detect said write operations during said current transfer operation, said coordinates module replacing said primary rectangle coordinates with said secondary rectangle coordinates for performing a subsequent transfer operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of modifying a design of a synchronous digital circuit comprising a plurality of clocked storage devices and a plurality of combinational logic elements defining combinational paths between at least some of said clocked storage devices, each combinational path from an output of a first one of said clocked storage devices to an input of a second one of said clocked storage devices having a minimum delay value and a maximum delay value, such that the actual delay of said path assumes a value between the minimum delay value and the maximum delay value, wherein the method comprises the steps of:
identifying among the combinational paths a combinational path having a greatest difference between the maximum delay value and the minimum delay value, and
reducing said difference between the maximum delay value and the minimum delay value by increasing the minimum delay value for said combinational path having the greatest difference.
2. A method according to claim 1, wherein the greatest difference in case of parallel paths is calculated as a difference between the highest maximum delay value and the lowest minimum delay value of the parallel paths.
3. A method according to claim 2, wherein the maximum delay value for a sequential path is calculated as a sum of the maximum delay values for the paths comprised in the sequential path, and wherein the minimum delay value for a sequential path is calculated as a sum of the minimum delay values for the paths comprised in the sequential path.
4. A method according to claim 1, wherein the step of increasing the minimum delay value for a combinational path is performed by inserting a plurality of buffers in the combinational path.
5. A method according to claim 1 comprising:
identifying among sequential paths from an input to an output of the circuit and sequential paths defining loops in the circuit a sequential path having a highest mean value of the maximum delay values,
calculating said highest mean value of the maximum delay values,
identifying those paths for which a difference between the maximum delay value and the minimum delay value exceeds said highest mean value of the maximum delay values, and
reducing said differences exceeding the highest mean value of the maximum delay values to be less than or equal to said highest mean value of the maximum delay values.
6. A system for modifying the design of a synchronous digital circuit comprising a plurality of clocked storage devices and a plurality of combinational logic elements defining combinational paths between at least some of said clocked storage devices, each combinational path from an output of a first one of said clocked storage devices to an input of a second one of said clocked storage devices having a minimum delay value and a maximum delay value, such that an actual delay of said path assumes a value between the minimum delay value and the maximum delay value, wherein the system comprises
means for identifying among the combination paths a combinational path having a greatest difference between the maximum delay value and the minimum delay value, and
means for reducing said difference between the maximum delay value and the minimum delay value by increasing the minimum delay value for said combinational path having the greatest difference.
7. A system according to claim 6, wherein the system is adapted to calculate the greatest difference in case of parallel paths as the difference between the highest maximum delay value and the lowest minimum delay value.
8. A system according to claim 7, wherein the system is adapted to calculate the maximum delay value for a sequential path as the sum of the maximum delay values for the paths comprised in the sequential path, and to calculate the minimum delay value for a sequential path as the sum of the minimum delay values for the paths comprised in the sequential path.
9. A system according to claim 6, wherein the system is adapted to increase the minimum delay value for a combinational path by the insertion of a plurality of buffers in the combinational path.
10. A system according to claim 6, wherein the system comprises
means for identifying among sequential paths from an input to an output of the circuit and sequential paths defining loops in the circuit the sequential path having the highest mean value of the maximum delay values,
means for calculating said highest mean value of the maximum delay values,
means for identifying those paths for which a difference between the maximum delay value and the minimum delay value exceeds said highest mean value of the maximum delay values, and
means for reducing said differences exceeding the highest mean value of the maximum delay values to be less than or equal to said highest mean value of the maximum delay values.
11. (canceled)
12. A machine readable medium comprising instructions for causing a processing unit to modify a design of a synchronous digital circuit including a plurality of clocked storage devices and a plurality of combinational logic elements defining combinational paths between at least some of said clocked storage devices, each combinational path from an output of a first one of said clocked storage devices to an input of a second one of said clocked storage devices having a minimum delay value and a maximum delay value such that the actual delay of said path assumes a value between the minimum delay value and the maximum delay value, wherein the instructions cause the processing unit to perform:
identifying the combinational path having the greatest difference between the maximum delay value and the minimum delay value; and
reducing said difference between the maximum delay value and the minimum delay value by increasing the minimum delay value for said combinational path having the largest difference.
13. The medium of claim 12, wherein the medium comprises instructions for causing the processing unit to calculate the greatest difference in case of parallel paths as a difference between a highest maximum delay value and a lowest minimum delay value.
14. The medium of claim 13, wherein the medium comprises instructions for causing the processing unit to:
calculate a maximum delay value for a sequential path as a sum of maximum delay values for paths comprised in the sequential path; and
calculate a minimum delay value for the sequential path as a sum of minimum delay values for paths comprised in the sequential path.
15. The medium of claim 12, wherein the medium comprises instructions for causing the processing unit to increase a minimum delay value for a combinational path by inserting a plurality of buffers in the combinational path.
16. The medium of claim 12, wherein the medium comprises instructions for causing the processing unit to perform:
identifying among sequential paths from an input to an output of the circuit and sequential paths defining loops in the circuit the sequential path having the highest mean value of the maximum delay values,
calculating said highest mean value of the maximum delay values,
identifying those paths for which a difference between a maximum delay value of the path and a minimum delay value of the path exceeds said highest mean value of the maximum delay values, and
reducing said differences exceeding the highest mean value of the maximum delay values to be less than or equal to said highest mean value of the maximum delay values.