1. A method of transmitting data, the method comprising:
transmitting a reference signal sequence r(m) to a terminal, wherein a first transmission point determines the reference signal sequence r(m) as follows:
r
\u2061
(
m
)
=
1
2
\u2062
(
1
–
2
\xb7
c
\u2061
(
2
\u2062
\u2062
m
)
)
+
j
\u2062
1
2
\u2062
(
1
–
2
\xb7
c
\u2061
(
2
\u2062
\u2062
m
+
1
)
)
,
wherein m an RB (resource block) corresponding to a frequency bandwidth of a downlink channel, and c( ) denotes a pseudo-random sequence, wherein an initial value, cinit, of the pseudo-random sequence is determined as follows:
cinit=(\u2514ns2\u2518+1)\xb7(2X+1)\xb7216+Y,
wherein ns is a slot number in a radio frame, X is a first initial value determining parameter, and Y is a second initial value determining parameter, and wherein ns is determined based on a slot number of a radio frame transmitted from a second transmission point to the terminal.
2. The method of claim 1,
wherein the first initial value determining parameter of the first transmission point is determined based on the first initial value determining parameter of the second transmission point to be the same as the first initial value determining parameter of the second transmission point, and
wherein the second initial value determining parameter of the first transmission point is determined based on the second initial value determining parameter of the second transmission point to be the same as the second initial value determining parameter of the second transmission point.
3. The method of claim 1, further comprising:
determining a UE-specific search space by the first transmission point, wherein the UE-specific search space is determined based on a slot number of the second transmission point.
4. The method of claim 1,
wherein the reference signal is a DM-RS (demodulation reference signal) for demodulating control information including downlink assignment and uplink grant information, and the cinit of the DM-RS is used as cinit of a URS (UE-specific reference signal) that is a reference signal for demodulating traffic data.
5. The method of claim 1,
wherein the second initial value determining parameter is a value set depending on whether a cell corresponding to the first transmission point is a primary cell.
6. The method of claim 1,
wherein the second initial value determining parameter varies depending on data transmission methods of the first transmission point.
7. A first base station transmitting data in a wireless communication system, the first base station comprising:
a processor configured to transmit a reference signal sequence r(m) to a terminal, wherein the processor determines the reference signal sequence r(m) as follows:
r
\u2061
(
m
)
=
1
2
\u2062
(
1
–
2
\xb7
c
\u2061
(
2
\u2062
\u2062
m
)
)
+
j
\u2062
1
2
\u2062
(
1
–
2
\xb7
c
\u2061
(
2
\u2062
\u2062
m
+
1
)
)
,
wherein m an RB (resource block) corresponding to a frequency bandwidth of a downlink channel, and c( ) denotes a pseudo-random sequence, wherein an initial value, cinit, of the pseudo-random sequence is determined as follows:
cinit=(\u2514ns2\u2518+1)\xb7(2X+1)\xb7216+Y,
wherein ns is a slot number in a radio frame, X is a first initial value determining parameter, and Y is a second initial value determining parameter, and wherein ns is determined based on a slot number of a radio frame transmitted from a second base station to the terminal.
8. The first base station of claim 7,
wherein the first initial value determining parameter of the first base station is determined based on the first initial value determining parameter of the second base station to be the same as the first initial value determining parameter of the second base station, and
wherein the second initial value determining parameter of the first base station is determined based on the second initial value determining parameter of the second base station to be the same as the second initial value determining parameter of the second base station.
9. The first base station of claim 7,
wherein the processor is configured to determine a UE-specific search space, and wherein the UE-specific search space is determined based on a slot number of the second base station.
10. The first base station of claim 7,
wherein the reference signal is a DM-RS (demodulation reference signal) for demodulating control information including downlink assignment and uplink grant information, and
wherein the cinit of the DM-RS is used as cinit of a URS (UE-specific reference signal) that is a reference signal for demodulating traffic data.
11. The first base station of claim 7,
wherein the second initial value determining parameter is a value set depending on whether a cell corresponding to the first base station is a primary cell.
12. The first base station of claim 7,
wherein the second initial value determining parameter varies depending on data transmission methods of the first base station.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor structure comprising:
a transistor formed in a semiconductor substrate, said semiconductor substrate having a semiconductor-on-insulator (SOI) layer;
a channel associated with said transistor and formed on a first portion of said SOI layer; and
a sourcedrain region associated with said transistor and formed in a second portion of said SOI layer and in a recess at each end of said channel, wherein said second portion of said SOI layer is substantially thicker than said first portion of said SOI layer; and wherein said sourcedrain region includes a stressor material.
2. The semiconductor structure of claim 1, further comprising a high-k metal gate disposed above said channel.
3. The semiconductor structure of claim 2, further comprising a sourcedrain extension formed between said channel and a corresponding said sourcedrain region, each said sourcedrain extension and said corresponding sourcedrain region being aligned to said high-k metal gate and said channel.
4. The semiconductor structure of claim 1, wherein said SOI layer is formed over a stair-shaped buried insulating (BOX) layer.
5. The semiconductor structure of claim 1, wherein said semiconductor structure further includes a BOX layer and formed over a base substrate layer, wherein said SOI layer is formed over said BOX layer.
6. The semiconductor structure of claim 1, wherein said stressor material is selected from a group consisting of eSiGe, eSi:C and a combination thereof.
7. The semiconductor structure of claim 1, wherein said stressor material in said sourcedrain region is substantially thicker than said first portion of said SOI layer.
8. The semiconductor structure of claim 1, wherein said first portion of said SOI layer includes a thickness ranging from about 5.0 nm to about 70.0 nm, and wherein said second portion of said SOI layer includes a thickness ranging from about 20.0 nm to about 70.0 nm.
9. The semiconductor structure of claim 1, wherein said first portion of said SOI layer includes a thickness ranging from about 5.0 nm to about 70.0 nm.
10. The semiconductor structure of claim 1, wherein said transistor is a strained filed effect transistor (FET).
11. A semiconductor device comprising:
a field effect transistor including:
a thin channel formed in a first portion of a semiconductor-on-insulator (SOI) layer;
a high-k metal gate disposed above said thin channel; and
a sourcedrain region formed in a second portion of said SOI layer and in a recess at each end of said thin channel, wherein said second portion of said SOI layer is substantially thicker than said first portion of said SOI layer; and
a stair-shaped buried insulating (BOX) layer insulating said SOI layer from a base semiconductor substrate;
wherein said sourcedrain region includes a stressor material selected from a group consisting of eSiGe, eSi:C and a combination thereof;
wherein said stressor material is substantially thicker that said first portion of said SOI layer.
12. The semiconductor structure of claim 11, further comprising a sourcedrain extension formed between said thin channel and said stressor material.
13. The semiconductor structure of claim 12, wherein each of said sourcedrain extension and said corresponding stressor material is aligned to said metal gate and said thin channel.
14. The semiconductor structure of claim 11, further comprising a sourcedrain extension formed between said channel and a corresponding said sourcedrain region, each said sourcedrain extension and said corresponding sourcedrain region being aligned to said high-k metal gate and said channel.
15. The semiconductor structure of claim 11, wherein said stressor material includes a thickness ranging from about 20.0 nm to about 70.0 nm.
16. The semiconductor structure of claim 11, wherein said first portion of said SOI layer includes a thickness ranging from about 5.0 nm to about 70.0 nm.
17. The semiconductor structure of claim 11, wherein said first portion of said stressor material includes a thickness ranging from about 20.0 nm to about 70.0 nm, and wherein said second portion of said SOI layer includes a thickness ranging from about 20.0 nm to about 70.0 nm.
18. The semiconductor structure of claim 11, wherein said first portion of said SOI layer includes a thickness ranging from about 5.0 nm to about 70.0 nm, and wherein said second portion of said SOI layer includes a thickness ranging from about 20.0 nm to about 70.0 nm.
19. A method of forming a semiconductor structure, the method comprising:
forming a dummy gate in a semiconductor substrate;
performing a SIMOX process to form a semiconductor-on-insulator (SOI) layer such that a first portion of said SOI layer under said dummy gate is substantially thinner than a second portion of said SOI layer;
forming a sourcedrain extension in said SOI layer; and
recessing said sourcedrain extension for forming a sourcedrain region;
epitaxially growing said second portion of said SOI layer;
forming an insulating layer over said epitaxial growth;
removing said dummy gate for forming a gate opening; and
filling said gate opening with a gate dielectric material and a gate conductor material.
20. The method recited in claim 19, wherein said SOI layer is formed over a stair-shaped buried insulating (BOX) layer.
21. The method recited in claim 19, wherein said sourcedrain region includes a stressor material.
22. The method recited in claim 19, wherein said stressor material is selected from a group consisting of eSiGe, eSi:C and a combination thereof.
23. The method recited in claim 19, wherein said first portion of said SOI layer includes a thickness ranging from about 5.0 nm to about 70.0 nm, and wherein said second portion of said SOI layer includes a thickness ranging from about 20.0 nm to about 70.0 nm.
24. The method recited in claim 19, wherein said first portion of said SOI layer includes a thickness ranging from about 5.0 nm to about 70.0 nm.
25. A method of forming a semiconductor structure, the method comprising
forming a dummy gate in thinned portion of a semiconductor-on-insulator (SOI);
forming sourcedrain extensions in said SOI layer abutting said thinned portion of said SOI layer;
forming an interlayer dielectric;
removing said dummy gate for forming a gate opening; and
forming a gate dielectric and a gate conductor in said gate opening;
wherein said SOI layer is formed over a stair-shaped buried insulating (BOX) layer.