1. A system comprising a neural process specification and a neural computing environment, said neural process specification further comprising a plurality of modules and a plurality of links for conveying signals there between, said neural computing environment executing said neural process specification.
2. The system of claim 1, wherein the system is configured to perform a cognitive function.
3. The system of claim 2, wherein the cognitive function is at least one of sensing, perception, reacting, learning, pattern recognition, short-term memory, working memory, long-term memory, classification, prediction, imagination, reasoning, planning, problem solving, acquiring and using skills, behavior, learning and navigating spaces, and language acquisition, understanding and generation.
4. The system of claim 1, wherein a link is a directed link comprising a source end and a target end, wherein a module connected to the source end sends signals over the directed link to a module connected to the target end, the target end-connected module being responsive to the signals.
5. The system of claim 4, wherein the source end-connected module and the target end-connected module are the same module.
6. The system of claim 4, wherein the directed link carries signals between the modules organizes the modules into a directed neural graph.
7. The system of claim 4, wherein the source end-connected module has at least one distinguished output port, the target end-connected module has at least one distinguished input port, the output port of the source end-connected module connects to the source end of the directed link, the target end of the link connects to an input port of the target end-connected module, the source end-connected module sends signals on the link via the output port, and the target end-connected module is responsive to the signals from the target end of the link connected to the input port.
8. The system of claim 1, wherein the signals comprise a plurality of events, each said event comprising a stamp, a signal identifier, and a signal value, where the stamp is selected from a group consisting of a real time value, a virtual time value, and a number, where the signal identifier uniquely identifies a signal among the signals on a link, and where the signal value is selected from the group consisting of a scalar, a vector, a matrix, a data structure, and a reference, each said event signifying a value of the signal identified by the signal identifier as of the stamp value.
9. The system of claim 1, wherein the neural process specification includes one or more parameters accessible to the plurality of modules.
10. The system of claim 9, wherein a module from the plurality of modules may change a value of one or more parameters of the neural process specification.
11. The system of claim 1, wherein a module from the plurality of modules additionally comprises one or more module parameters for specifying and controlling a function and operation of the module.
12. The system of claim 11, wherein a value of a module parameter is computed as a function of one or more parameters of the neural process specification.
13. The system of claim 1, wherein a module from the plurality of modules additionally maintains one or more internal state values, said state values being updated as appropriate to a function of said module.
14. The system of claim 1, wherein a module from the plurality of modules additionally accesses one or more external state values, said state values being accessible to other modules from the plurality of modules, and where said state values may be updated by one or more modules from the plurality of modules.
15. The system of claim 14, wherein one or more said external state values represents a long-term memory pattern.
16. The system of claim 1, wherein a module from the plurality of modules is an input module, performing an input function, obtaining external information from an external environment and conveying it as one or more said signals to a said link.
17. The system of claim 16, wherein said external information is selected from the group consisting of image, video, audio, MIDI, user input gesture, keystroke, phonetic stream, data stream, message stream, external program output, file reading, stochastic process observations, query results, search results, sensor reports, and sensor observations.
18. The system of claim 1, wherein a module from said plurality of modules is an output module, performing an output function, receiving one or more signals from a link and transmitting corresponding information to an external environment.
19. The system of claim 18, wherein the external information is selected from the group consisting of image, video, audio, MIDI, alphanumeric text, symbolic text, visual display, file writing, data stream, message stream, external program input, database update, control of mechanisms, control of apparatus, and voice synthesis.
20. The system of claim 1, wherein a module from said plurality of modules is a processing module, receiving one or more signals from an input link, performing a module function specific computation, and as determined by said computation, sending signals on an output link.
21. The system of claim 20, wherein the module is at least one of a transformer module, a filter module, a working memory module, a group operations module, a wrapper module, a sub-graph module and a custom program module.
22. The system of claim 1, wherein said neural process specification further comprises one or more pattern memory spaces, each said memory pattern space holding one or more memory patterns, each said memory pattern representing a combination of signal values, and each said memory space being sharable by one or more said modules in the neural process specification.
23. The system of claim 22, wherein at least one module is a memory pattern module accessing one or more memory patterns in one or more said memory pattern spaces.
24. The system of claim 23, wherein said memory module compares a combination of input signals with a memory pattern in said plurality of memory patterns, deriving for said memory pattern a pattern matching score reflecting a degree of matching of said input signal combination with said memory pattern and sends an output signal for said pattern using a function of said pattern matching score as the signal value.
25. The system of claim 24, wherein said function is one of a constant function, a binary function, a linear function, a logistic function or mathematical combinations thereof.
26. The system of claim 23, wherein said module additionally creates a new memory pattern corresponding to an input signal combination on said input links that fails to match any existing said memory pattern with a matching score above a threshold value.
27. The system of claim 23, wherein said module additionally makes adjustments to a memory pattern to incorporate an input signal combination, a magnitude of said pattern adjustments governed by a learning rate.
28. The system of claim 27, wherein said adjustments include one of changing a weight associated with an input signal, changing an expected value associated with an input signal, adding a new signal to the memory pattern, and removing a signal from the memory pattern.
29. The system of claim 24, wherein said module is at least one of a set module, a sequence module or a temporal module.
30. The system of claim 29, wherein a said module is selected from a group consisting of a weight set module and a weight value set module.
31. The system of claim 29, wherein a said module is selected from a group consisting of a weight matrix sequence pattern module, a weight value matrix sequence pattern module, a regular expression sequence pattern module, an edit distance sequence pattern module, an open bigrams sequence pattern module, and a state machine sequence pattern module.
32. The system of claim 24, wherein a said module is a temporal module.
33. The system of claim 22, wherein a said module is a reify module for generating output signals corresponding to identifiers in a pattern which pattern identity is received as an input signal.
34. The system of claim 1, wherein the neural computing environment comprises a compilation function, an executable process representation, and an execution machine, where said compilation function generates said executable process representation corresponding to said neural process specification and said execution machine executes said executable process representation.
35. The system of claim 34, wherein said executable process representation is a machine language representation and where said process execution machine comprises one or more physical or virtual computer processors for running said machine language representation.
36. The system of claim 34, wherein said executable process representation involves multiprocessor coordination.
37. The system of claim 35, wherein said executable process representation is a configuration specification for configuring hardware to perform the functions of the neural process specification.
38. The system of claim 1, wherein the neural computing environment comprises a neural process specification interpreter and executable module implementations, said interpreter and module implementations further using facilities of a computer operating system and one or more computer processors to execute the neural process specification.
39. The system of claim 38, wherein the processing of the executable module implementation of said module may be performed on multiple computer processors.
40. The system of claim 38, wherein the processing of functions of multiple interconnected modules may be split among multiple computer processors organized as one or more of a shared-memory multi-processor system, a non-shared-memory multi-processor system, and a distributed system.
41. The system of claim 1, wherein the neural computing environment allocates modules and links of a said neural processing specification to processing nodes and communications paths in a multi-processor or distributed computing system.
42. The system of claim 41, wherein said allocation of modules and links can change during the execution of the neural process specification.
43. The system of claim 41, wherein said allocation of modules and links includes redundant execution of parts of a neural process specification.
44. The system of claim 1, wherein the neural computing environment maintains a monotonically non-decreasing virtual time clock which may advance at least one of faster, slower and at the same rate as real time wherein stamp values of events are set and interpreted relative to said virtual time clock.
45. The system of claim 1, wherein the neural computing environment continues execution of parts of a neural process specification when execution of other parts stop operating or stop communicating.
46. The system of claim 1 further comprising a development environment further comprising a library of said module types, an external persistent representation of a neural processing specification, and a user interface for creating, modifying, saving and restoring a said neural processing specification.
47. The system of claim 46 further comprising a user interface for assembling and modifying a neural process specification graphically in a directed graph form by one or more of adding a module, configuring a module, removing a module, adding a link, configuring a link and removing a link.
48. The system of claim 46 further comprising a user interface whereby a developer may assemble and modify a neural process specification graphically using a block construction visual metaphor by placing blocks representing module instances on a design canvas and representing links by block proximity.
49. The system of claim 46 further comprising a user interface for setting and modifying parameters of a said module instance.
50. The system of claim 46 further comprising a graphical user interface for setting and modifying parameters of said neural process specification.
51. The system of claim 46, wherein a visual editor provides a zoom function to vary a display of sub-graphs of the neural process specification wherein such variation may include at least one of expansion, contraction, separation, and hiding of the display of at least one sub-graph.
52. The system of claim 46 further comprising at least one or more functions for deploying a neural process specification for execution by a said neural computing environment, starting, controlling, monitoring, pausing, continuing or stopping execution of a neural process specification.
53. The system of claim 46 further comprising a facility to vary a rate at which a neural process executes.
54. The system of claim 46 further comprising facilities for at least one of tracing and displaying aspects of the execution of a neural process.
55. The system of claim 46, wherein design changes made to said neural process specification change the execution of said neural process while executing.
56. The system of claim 46 further comprising displaying changing aspects of neural process execution using visual attributes of icons and lines.
57. The system of claim 46 further comprising a graphical representation of one or more memory patterns.
58. A system comprising a neural process specification and a neural computing environment, said neural process specification further comprising at least one module.
59. The system of claim 58, wherein the at least one module has no links to external modules and performs at least one neural process computing function that is internal to the module.
60. The system of claim 58 further comprising at least one link of the module for conveying signals at least one of to the at least one module and from the at least one module, said neural computing environment executing said neural process specification.
61. The system of claim 60, wherein the at least one module is configured to mimic a cognitive function of a biological brain.
62. The system of claim 61, wherein the cognitive function is at least one of sensing, perception, reacting, learning, pattern recognition, short-term memory, working memory, long-term memory, classification, prediction, imagination, reasoning, planning, problem solving, acquiring and using skills, behavior, learning and navigating spaces, and language acquisition, understanding and generation.
63. The system of claim 60, wherein the system comprises a single source module that undertakes a function and provides an output via a link.
64. The system of claim 60, wherein the system comprises a single target module that takes an input via a link and performs a function.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A time slot interchange switch, comprising:
a serial to parallel converter receiving at least one serial data stream and converting serial channel data in the at least one serial data stream into parallel channel data;
a data memory coupled to the serial to parallel converter to receive and store the parallel channel data, the parallel channel data including a bit error rate channel having bit error rate channel data;
a connection memory coupled to the data memory, wherein data is read out of data memory in response to addressing data stored in the connection memory;
a memory controller coupled to the data memory to control readout of the bit error rate channel received by the data memory;
a bit error rate receiver coupled to the data memory and the memory controller, the bit error rate receiver receiving the bit error rate channel from the data memory, converting the bit error rate channel data to serial data, and calculating a bit error rate;
a bit error rate transmitter coupled to the memory controller and a multiplexer through a latch, the bit error rate transmitter generating a burst signal for output from the time slot interchange switch in response to a request signal received from the memory controller; and
a register block coupled to receive and store the bit error rate channel in a first register and store an address where the bit error rate channel is stored in the data memory.
2. The time slot interchange switch of claim 1, wherein the multiplexer can output channel data from the data memory or channel data generated by the bit error rate transmitter, the bit error rate transmitter generating a pseudo random number generated channel data in a time slot determined by an address stored in a third register of the register block.
3. A method of performing bit error rate testing in a time slot interchange switch, comprising:
receiving parallel bit error rate data for a bit error rate data channel;
storing the parallel bit error rate data in a data memory;
reading the parallel bit error rate data from the data memory in accordance with an address stored in a first register of a register block;
converting the parallel bit error rate data to serial bit error rate data and calculating a bit error rate;
storing the bit error rate in a second register in the register block; and further including:
generating a channel data appropriate for a bit error rate test; and
outputting the channel data appropriate for a bit error rate test in an output data stream according to an address stored in a third register of the register block.
4. The method of claim 3, further including reading the bit error rate from the second register in the register block to a microprocessor.