1. A method for an interruptible graphics processing unit (\u201cGPU\u201d) to process multiple programs, comprising the steps of:
receiving a first run list containing a plurality of contexts for execution;
initiating processing of a buffer containing commands and data associated with a context in the first run list, the data including a primitive identifier, a tile identifier, and an instance identifier corresponding to a processing status at the moment of receipt of an interrupt command, the primitive identifier defining an interrupted primitive, the tile identifier defining an interrupted tile, and the instance identifier defining a point of interrupt in an interrupted draw command;
retrieving a GPU memory access command from the buffer and a pointer referencing graphics data associated with the buffer;
communicating the pointer to one or more architectural processing units in the GPU for accessing register states;
switching to another buffer of the first run list for processing data associated with the another buffer; and
switching to another run list when a final buffer in the run list is empty.
2. The method of claim 1, further comprising the step of:
determining whether the buffer contains a restore command and fetching saved state data from memory associated to the buffer if the buffer contains a restore command.
3. The method of claim 1, further comprising the step of:
fetching a head and tail pointer associated with a buffer and determining whether a predetermined logical position in the buffer is a skip or restore command such that saved state data is retrieved from memory if the predetermined logical position is a restore command.
4. The method of claim 1, further comprising the step of:
processing a current location in the buffer according to the executed GPU memory access command.
5. The method of claim 1, further comprising the steps of:
forwarding from a command processor to a triangle setup unit in a processing pipeline of the GPU a memory access offset value and register states corresponding to the processing of data associated with the buffer; and
forwarding the instance identifier, the primitive identifier, and the tile identifier to a processing unit for processing data associated with the buffer.
6. The method of claim 1, further comprising the steps of:
forwarding from a command processor to a triangle setup unit in a processing pipeline of the GPU a triangle ID associated with a tessellated primitive.
7. The method of claim 1, further comprising the step of:
determining whether a head pointer associated with a point of processing of the buffer is equal to a tail pointer associated with the buffer;
designating the buffer as being empty if the head pointer equals the tail pointer; and
processing one or more draw and GPU function commands contained in a buffer referenced by the pointer if the head pointer does not equal the tail pointer.
8. The method of claim 7, further comprising the step of:
processing all GPU function commands in the buffer so that the head pointer moves in a logical direction that is closer to the tail pointer until obtaining the same logical value as the tail pointer.
9. The method of claim 7, further comprising the step of:
moving the tail pointer to a new logical position if one or more additional GPU function commands or pointers are added to the buffer.
10. A graphics processing unit (\u201cGPU\u201d) configured for processing a plurality of programs, comprising;
a processor for controlling the processing of data by a graphics pipeline coupled to the processor;
logic configured to establish a run list of contexts for execution;
logic configured to retrieve one or more commands and one or more pointers associated with a first context for execution by the graphics pipeline, the one or more pointers including a primitive identifier, a tile identifier, and an instance identifier corresponding to a processing status at the moment of receipt of an interrupt command, the primitive identifier defining an interrupted primitive, the tile identifier defining an interrupted tile, and the instance identifier defining a point of interrupt in an interrupted draw command;
logic configured for the processor to forward the one or more commands and the one or more pointers to the graphics pipeline for processing by the graphics pipeline, wherein data associated with the one or more commands and the one or more pointers, are executed by the graphics pipeline until interrupted or until the first context is empty; and
logic configured to switch the processor to another context in the run list or to another run list if all contexts in the run list are empty.
11. The GPU of claim 10, further comprising:
logic configured to communicate the one or more pointers from a front end parser in the processor to the graphics pipeline.
12. The GPU of claim 10, further comprising:
logic configured to retrieve a head and tail pointer associated with a first context in the run list and a memory access command if the head pointer does not equal the tail pointer.
13. The GPU of claim 12, further comprising:
logic configured to move the tail pointer to a new logical position if one or more additional commands or pointers are added to the first context.
14. The GPU of claim 10, further comprising:
logic configured to determine if the head pointer equals the tail pointer after execution of a command, wherein an end of context determination is made if the head pointer equals the tail pointer, and wherein a next command or pointer is obtained if the head pointer does not equal the tail pointer.
15. The GPU of claim 10, further comprising:
logic configured to determine whether a current context contains a restore command in a data structure being processed and to retrieve all state data associated with a restored state and context if the data structure does contain a restore command.
16. The GPU of claim 15, further comprising:
logic configured to retrieve one or more memory access commands associated with the restored state of the current context and to process the current context associated with restored state to completion.
17. The GPU of claim 16, further comprising:
logic configured to switch to a next context in the run list when the current context associated with restored state is complete.
18. The GPU of claim 16, wherein the one or more memory access commands are forwarded to one or more architectural units in the graphics pipeline that operate to resume processing on the restored state and context at a precise point where previously interrupted.
19. The GPU of claim 10, further comprising:
logic configured to communicate an interrupt command to a central processor coupled to the GPU when the first context is complete.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-15. (canceled)
16. An apparatus for plating a substrate having a plating surface to be plated, said apparatus comprising:
a plating vessel accommodating a plating solution and an anode therein and having a lateral opening;
a substrate holder for holding said substrate while exposing said plating surface to said plating solution within said plating vessel and sealing said substrate to prevent infiltration of plating solution to a surface of said substrate other than said exposed plating surface; and
a holder driving assembly for driving said substrate holder to a position where said plating surface covers said opening of said plating vessel.
17. The apparatus of claim 16, wherein said substrate holder is laterally slidable.
18. The apparatus of claim 16, wherein said plating vessel comprises a weir member for confining a reservoir surrounding said anode within said plating vessel, which can contain plating solution therein for immersing said anode.
19. The apparatus of claim 18, further comprising an auxiliary plating solution supply system for circulating said plating solution within said reservoir chamber.
20. The apparatus of claim 16, further comprising a rapid drain system for rapidly draining plating solution from said plating vessel.
21. The apparatus of claim 16, further comprising a nozzle for ejecting plating solution toward said plating surface of said substrate held by said substrate holder.
22. The apparatus of claim 16, wherein said substrate holder comprises a detachable seal unit comprising a seal ring and a cathode integrated together.
23. The apparatus of claim 22, wherein said seal unit comprises a seal member for water-tightly sealing said opening of said plating vessel.
24. A method of plating a substrate having a plating surface to be plated, said method comprising:
accommodating a plating solution and an anode in a plating vessel having a lateral opening;
holding said substrate with a substrate holder while exposing said plating surface to said plating solution within said plating vessel and sealing said substrate to prevent infiltration of plating solution to a surface of said substrate other than said exposed plating surface; and
driving said substrate holder to a position where said plating surface covers said opening of said plating vessel.
25. The method of claim 24, wherein said plating vessel comprises a weir member for confining a reservoir surrounding said anode within said plating vessel, said method comprising immersing said anode by introducing plating solution within said reservoir.
26. The method of claim 24, further comprising rapidly draining plating solution from said plating vessel after plating is finished.