1. A method for receiver optimization in a receiver with bypassable decimation filters, comprising:
injecting a signal into an input of the receiver;
enabling a bypass select enable for the decimation filters such that the signal bypasses the decimation filters;
optimizing a programmable gain amplifier; and
disabling the bypass select enable for the decimation filters, wherein the step of optimizing the programmable gain amplifier further comprises:
A. selecting a sampling phase out of a set of sampling phases;
B. configuring sampling phase selects for a downsampling circuit corresponding to the selected sampling phase;
C. downsampling the signal, producing a downsampled signal;
D. measuring signal power of the downsampled signal;
E. repeating the steps A\u2013D for remaining sampling phases;
F. combining measured signal powers of downsampled signals, producing a measured signal power of the signal; and
G. adjusting gain of the programmable gain amplifier according to the measured signal power of the signal.
2. The method of claim 1, wherein the signal is a periodic signal with Gaussian noise characteristics.
3. The method of claim 1, wherein the step of combining the measured signal powers is accomplished by adding the measured signal powers derived at step D and then multiplying the result of the addition with a scaling factor.
4. The method of claim 1, wherein the step of combining the measured signal powers is accomplished by averaging the measured signal powers derived at step D.
5. The method of claim 1 and further comprises the step of optimizing sampling phase.
6. The method of claim 5, wherein the step of optimizing sampling phase further comprises:
A. zeroing a maximum power value and an optimal phase value and a current phase value;
B. selecting a sampling phase out of a set of sampling phases and setting the current phase value equal to the selected sampling phase;
C. configuring sampling phase selects for a downsampling circuit corresponding to the current phase value;
D. downsampling the signal, producing a downsampled signal;
E. calculating a Fourier Transform of the downsampled signal;
F. measuring signal power at a frequency range around a frequency of interest;
G. comparing the measured signal power with the maximum power value;
H. setting the maximum power value equal to the measured signal power if the measured signal power is greater than the maximum power value;
I. setting the optimal phase value equal to the current phase value if the measured signal power is greater than the maximum power value;
J. repeating the steps B\u2013I for remaining sampling phases in set of sampling phases; and
K. setting the sampling phase selects for the downsampling circuit corresponding to the optimal phase value.
7. The method of claim 5, wherein the step of optimizing sampling phase further comprises:
A. calculating a Fourier Transform of the signal;
B. selecting a sampling phase from a set of sampling phases;
C. configuring sampling phase selects for a downsampling circuit corresponding to the selected sampling phase;
D. computing a channel response at the Nyquist frequency;
E. calculating an error function for the selected sampling phase;
F. repeating steps B\u2013E for remaining sampling phases in the set of sampling phases; and
G. selecting the sampling phase resulting in the minimal error function.
8. The method of claim 7, further comprising the step of downsampling the signal prior to taking the Fourier Transform.
9. The method of claim 7, wherein computing the channel response at the Nyquist frequency is dividing a received signal at the Nyquist frequency by the signal at the Nyquist frequency.
10. The method of claim 7, wherein the error function is the absolute value of the difference of a real component of the channel response at the Nyquist frequency and an imaginary component of the channel response at the Nyquist frequency.
11. The method of claim 7, wherein the error function is \xbd of a maximum received signal power minus the channel response at the Nyquist frequency.
12. The method of claim 5, wherein the step of optimizing sampling phase further comprises:
calculating a Fourier Transform of the signal;
computing a channel response at the Nyquist frequency;
estimating the channel response for each sampling phase in the set of sampling phases based on the computed channel response;
calculating an error function for said each estimated channel response; and
selecting the sampling phase resulting in the minimal error function.
13. The method of claim 12, wherein the estimating a channel response for a sampling phase is performed using the equation:
H(N2, p)=H(N2, 0)* exp(j*\u03c0*pL)
where p is the sampling phase desired, \u03c0 is pi, L is the number of possible sampling phases, H(N2, 0) is the computed channel response at the Nyquist frequency, and N and L are integers.
14. A method for optimizing sampling phase in a receiver with bypassable decimation filters, comprising:
A. disabling a bypass select enable for the bypassable decimation filters;
B. injecting a signal into the receiver’s input;
C. zeroing a maximum power value and an optimal phase value and a current phase value;
D. selecting a sampling phase out of a set of sampling phases and setting current phase value equal to said selected sampling phase;
E. configuring sampling phase selects for a downsampling circuit corresponding to the current phase value;
F. downsampling the signal, producing a downsampled signal;
G. calculating a Fast Fourier Transform of the downsampled signal;
H. measuring signal power at a frequency range around a frequency of interest;
I. comparing the measured signal power with the maximum power value;
J. setting the maximum power value equal to the measured signal power if the measured signal power is greater than the maximum power value;
K. setting the optimal phase value equal to the current phase value if the measured signal power is greater than the maximum power value;
L. repeating the steps D\u2013K for remaining sampling phases in the set of sampling phases; and
M. setting the sampling phase selects for the downsampling circuit corresponding to the optimal phase value.
15. The method of claim 14, wherein the frequency of interest is 138 kilohertz.
16. The method of claim 14, wherein the Fast Fourier Transform is a 128-point Fast East Transform.
17. The method of claim 14, wherein the set of sampling phases is the set of all possible sampling phases.
18. A method for optimizing sampling phase in a receiver with bypassable decimation filters, comprising:
A. disabling a bypass select enable for the bypassable decimation filters;
B. injecting a signal into the receiver’s input;
C. downsampling the signal;
D. calculating a Fast Fourier Transform of the decimated signal;
E. selecting a sampling phase from a set of sampling phases;
F. configuring sampling phase selects for a downsampling circuit corresponding to the selected sampling phase;
G. computing a channel response at the Nyquist frequency;
H. calculating an error function for said selected sampling phase;
I. repeating steps E\u2013H for remaining sampling phases in the set of sampling phases; and
J. selecting the sampling phase resulting in the minimal error function.
19. The method of claim 18, wherein the error function is expressible as:
error function=real(channel response at Nyquist frequency)\u2212imaginary(channel response at Nyquist frequency).
20. The method of claim 18, wherein the error function is expressible as:
error function=abs(0.5*maximum signal power at Nyquist frequency\u2212abs(channel response at Nyquist frequency))
where abs( ) is the absolute value function.
21. The method of claim 18, wherein the Nyquist frequency may be approximated using the expression:
H(N2)=H(N2\u22121)*H(N2\u22121)(H(N2\u22122)
where H(N2\u22121) is the channel response at a frequency closest to the Nyquist frequency and H(N2\u22122) is the channel response at a frequency second closest to the Nyquist frequency.
22. A method for optimizing a programmable gain amplifier in a receiver with bypassable decimation filters, comprising the steps of:
A. enabling bypass select enable for the decimation filters;
B. injecting a signal into the receiver’s input;
C. selecting a sampling phase out of a set of sampling phases;
D. configuring sampling phase selects for a downsampling circuit corresponding to said selected sampling phase;
E. downsampling the signal, producing a downsampled signal;
F. measuring signal power of the downsampled signal;
G. repeating the steps C\u2013F for remaining sampling phases;
H. combining said measured signal powers of the downsampled signals, producing a measured signal power of the signal; and
I. adjusting gain of the programmable gain amplifier according to the measured signal power of the signal.
23. A method according to claim 22, wherein the step of combining all measured signal powers is accomplished by adding all the individual measured signal powers followed by multiplying the result of the addition with a scaling factor.
24. A method according to claim 22, wherein the downsampling circuit is a linear sequence of at least one downsampling circuit.
25. A circuit for sampling phase and programmable gain amplifier optimization in a receiver, comprising:
a data input for providing a datastream;
a data output;
a decimation filter, having an input coupled to the data input and an output, adapted to filter signal energy in downsampled signals;
a downsampler, having a first input coupled to the decimation filter and a second input and an output coupled to the data output, adapted to select a sample from each group of LN consecutive samples from the datastream, wherein LN is the downsampler’s downsampling rate;
a decimation filter bypass, having an input, adapted to allow the datastream to pass from the input to the first input of the downsampler without being filtered by the decimation filter;
a bypass select enable line, a control line coupled to the input of the decimation filter bypass, adapted to control the decimation filter bypass; and
a sampling phase select line, a select line coupled to the second input of the downsampler, adapted to specify which sample from a group of LN consecutive samples the downsampler should select, wherein LN is an integer.
26. The circuit of claim 25, wherein the datastream is a digital datastream.
27. A receiver comprising:
an analog front end for receiving analog signals;
a programmable gain amplifier, having an input coupled to the analog front end and an output, adapted to variably amplify the analog signal and output an amplified analog signal;
an analog-to-digital converter, having an input coupled to the programmable gain amplifier and an output, the analog-to-digital converter adapted to convert the amplified analog signal into a digital bitstream;
a circuit having a data input coupled to the analog-to-digital converter and an output, for sampling phase and programmable gain amplifier optimization, the circuit comprising:
a decimation filter, having an input coupled to the data input and an output, adapted to filter signal energy in downsampled signals;
a downsampler, having a first input coupled to the decimation filter and a second input and an output coupled to the output of the circuit, adapted to select a sample from each group of LN consecutive samples from the digital bitstream, wherein LN is the downsampler’s downsampling rate;
a decimation filter bypass, having an input, adapted to allow the digital bitstream to pass from the input to the first input of the downsampler without being filtered by the decimation filter;
a bypass select enable line, a control line coupled to the input of the decimation filter bypass, adapted to control the decimation filter bypass;
a sampling phase select line, a select line coupled to the second input of the downsampler, adapted to specify which sample from a group of LN consecutive samples the downsampler should select; and
the system further comprising a digital baseband processor, having an input coupled to the output of the circuit, the digital baseband processor adapted to receive downsampled digital data and convert the downsampled digital data into user data, wherein LN is an integer.
28. The system of claim 27, wherein the sampling phase and programmable gain amplifier optimization occurs during the system’s initialization phase.
29. The system of claim 27, wherein the system is comprised of a sequence of at least two linearly connected circuits.
30. The system of claim 29, wherein each linearly connected circuit downsamples the digital bitstream by a factor of 2.
31. A system according to claim 27, wherein the sampling phase and programmable gain amplifier optimization occurs periodically during the system’s operation.
32. A system according to claim 27, wherein the results of the sampling phase and programmable gain amplifier optimization is saved so that the optimization does not require repeating after initial optimization.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Embedded testing circuit for testing a dual port memory having a memory cell array being accessible through a first port and a second port, said embedded testing circuit comprising:
(a) an embedded address generation circuit for generating an internal address consisting of an internal row selection address and an internal column selection address in response to an external address consisting of an external row selection address and an external column selection address,
(a1) wherein said internal row selection address for addressing a second row of said memory cell array through said second port is generated by an adder which increments the external row selection address for addressing a first row of said memory cell array through said first port, such that the first row and said second row form adjacent rows within said memory cell array,
(a2) wherein said internal column selection address for addressing columns of said memory cell array through said second port is switchable to be identical to said external column selection address; and
(b) an embedded data generation circuit for generating an internal test data pattern in response to an external test data pattern,
wherein said external test data pattern for accessing said memory cell array through said first port is switchable to be inverted by an inverter when said memory cell array is accessed through said second port.
2. The embedded testing circuit according to claim 1, wherein said adder for incrementing said external row selection address comprises for each bit of said row selection address a corresponding adding element.
3. The embedded testing circuit according to claim 2, wherein for an external address having n bits consisting of m external column selection bits and external row selection bits, the adder comprises adding elements wherein each adding element is proyided for a corresponding external row selection bit of said external address.
4. The embedded testing circuit according to claim 3, wherein a first adding element of said adder provided for the first row selection bit is formed by an inverting circuit;
second to penultimate adding elements of said adders provided for the second to penultimate row selection bits are formed by logic units; and
a last adding element of said adder provided for the last row selection bit is formed by an EXOR-gate logic.
5. The embedded testing circuit according to claim 4, wherein each logic unit of said adder comprises an AND-gate for a logical AND-combination of the corresponding external row selection bit with an output of an AND-gate of a preceding logic unit of the adder; and
an EXOR-gate for a logical EXOR-combination of the corresponding external row selection bit with the output of the AND-gate of the preceding logic unit to generate a corresponding internal row selection bit for addressing said memory cell array.
6. The embedded testing circuit according to claim 5, wherein said embedded address generation circuit comprises for each generated internal row selection bit a address bit multiplexer which is switchable in response to an external switch control signal between a first input to which said generated internal row selection bit is applied by an adding element of said adder and a second input to which a separate external address bit for accessing said memory cell array through said second port is applied.
7. The embedded testing circuit according to claim 1, wherein said embedded address generation circuit comprises for each bit of said m external column selection bits of said external column selection address an address bit multiplexer which is switchable in response to an external selection control signal between a first input to which said external column selection bit for addressing a column of said memory cell array through said first port is applied and a second input to which a separate external address bit for accessing said memory cell array through said second port is applied.
8. The embedded testing circuit according to claim 1, wherein said dual port memory is a random access memory.
9. The embedded testing circuit according to claim 8, wherein the random access memory is a static random access memory.
10. The embedded testing circuit according to claim 1, wherein said first port and said second port is selected in response to a port selection control signal.
11. The embedded testing circuit according to claim 1, wherein said first port is clocked by a first external clock signal and said second port is clocked by a second external clock signal.
12. The embedded testing circuit according to claim 1, wherein an operation of said first port is controlled in response to a first external readwrite enable control signal and an operation of said second port is controlled in response to a second external readwrite enable control signal.
13. A testing system for testing dual port memories each having a memory cell array being accessible by a first port and a second port, said testing system comprising:
(a) an external tester for generating an external test address and an external test data pattern;
(b) at least one dual port memory which includes an embedded testing circuit having:
(b1) an embedded address generation circuit for generating an internal address consisting of an internal row selection address and an internal column selection address in response to an external address consisting of an external row selection address and an external column selection address,
(b2) wherein said internal row selection address for addressing a second row of said memory cell array through said second port is generated by an adder which increments the external row selection address for addressing a first row of said memory cell array through said first port, such that the first row and said second row form adjacent rows within said memory cell array,
(b3) wherein said internal column selection address for addressing columns of said memory cell array through said second port is switchable to be identical to said external column selection address; and
(c) an embedded data generation circuit for generating an internal test data pattern in response to said external test data pattern,
wherein said external test data pattern for accessing said memory cell array through said first port is switchable to be inverted by an inverter, when said memory cell array is accessed through said second port.
14. The testing system according to claim 13, wherein said external tester is connected to said at least one dual port memory via an address bus to apply said external test address to said dual port memories and via a data bus to exchange data with the addressed dual port memory.
15. The testing system according to claim 13, wherein said external tester is connected to said dual port memories via a first clock line to apply a first clock signal for the first port of said dual port memory and via a second clock line to apply a second clock signal for the second port of said dual port memory.
16. The testing system according to claim 13, wherein said external tester is connected to said dual port memory via a first selection control line to apply a first selection control signal to select said first port of said dual port memory and via a second selection control line to apply a second selection control signal to select said second port of said dual port memory.
17. The testing system according to claim 13, wherein said external tester is connected to said dual port memory via a first operation control line to apply a readwrite enable control signal to said first port of said dual port memory and via a second operation control line to apply a second readwrite enable control signal to said second port of said dual port memory.
18. A method for testing a dual port memory having a memory cell array being accessible through a first port and a second port, wherein the method comprises the following steps:
(a) generating an internal address consisting of an internal row selection address and an internal column selection address in response to an external address consisting of an external row selection address and an external column selection address, wherein said internal row selection address for addressing a second row of said memory cell array through said second port is generated by incrementing the external row selection address for addressing a first row of said memory cell array through said first port, such that said first row and said second row form adjacent rows of said memory cell array,
(b) wherein said internal column selection address for addressing columns of said memory cell array through said second port is formed to be identical to said external column selection address, and
(c) generating an internal test data pattern is response to an external test data pattern, wherein said external test data pattern for accessing said memory cell array through said first port is inverted when said memory cell array is accessed through said second port.