1. A micromechanical actuator, comprising:
a silicon-on-insulator substrate having a device layer formed in a plane;
a metallic material inlaid in the plane of the device layer and configured to move substantially in the plane of the device layer;
a silicon member formed from the device layer of a silicon-on-insulator substrate, configured to move substantially in the plane of the device layer, wherein movement of the inlaid material drives movement of the silicon member.
2. The micromechanical actuator of claim 1, wherein the inlaid material moves about a proximal end, the proximal end being anchored to the silicon-on-insulator substrate, when the inlaid material is heated.
3. The micromechanical actuator of claim 2, wherein the inlaid material extends substantially through the plane of the device layer, and is coupled at its distal end by a dielectric tether to an adjunct silicon portion.
4. The micromechanical actuator of claim 3, wherein the adjunct silicon portion is separated from the silicon member by an air gap in a quiescent state, and the inlaid material closes the air gap and drives movement of the silicon member when the micromechanical actuator is energized.
5. The micromechanical actuator of claim 4, wherein surfaces which define the air gap comprise at least one of silicon nitride, silicon dioxide, an inlaid metal, an inlaid semiconductor and a hydrofluoric acid etch-resistant polymer.
6. The micromechanical actuator of claim 1, further comprising a metal contact electrode which overhangs a wall on a distal end of the silicon member, the wall of the silicon member being disposed perpendicularly with respect to the plane of the device layer.
7. The micromechanical actuator of claim 1, further comprising a metal contact electrode inlaid in the plane of the device layer, and contiguous with a distal end of the silicon member.
8. A micromechanical switch comprising at least one micromechanical actuator of claim 1 and at least one additional micromechanical actuator, each micromechanical actuator configured to move substantially perpendicularly with respect to the other, in order to make contact between contact electrodes disposed on the distal ends of the micromechanical actuators.
9. An array of micromechanical switches, comprising at least one of the micromechanical switches of claim 1.
10. The array of micromechanical switches of claim 9, wherein electrical contact to the inlaid material is made by vias formed in the silicon-on-insulator substrate.
11. The array of micromechanical switches of claim 10, further comprising a lid wafer with at least one device cavity formed therein, which encloses the array of micromechanical switches.
12. The array of micromechanical switches of claim 11, wherein electrical contact to the micromechanical switches is made by vias formed through the thickness of the lid wafer.
13. The micromechanical actuator of claim 1, wherein, wherein the inlaid metallic material comprises at least one of a magnetically permeable material, gold, a gold alloy, nickel, a nickel alloy, aluminum, permalloy, platinum, and copper.
14. The micromechanical actuator of claim 6, wherein the contact electrode comprises at least one of gold, a gold alloy, rhodium, ruthenium, platinum, nickel, a nickel alloy, aluminum and copper, and the silicon member comprises single crystal silicon.
15. The micromechanical actuator of claim 1, wherein a top surface of the inlaid metallic material is substantially flush with a top surface of the device layer.
16. A micromechanical actuator, comprising:
a silicon-on-insulator substrate having a device layer formed in a plane;
a material inlaid in the plane of the device layer and configured to move substantially in the plane of the device layer;
a silicon member formed from the device layer of a silicon-on-insulator substrate, configured to move substantially in the plane of the device layer, wherein movement of the inlaid material drives movement of the silicon member,
wherein the silicon member is clad with a metal contact material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method implemented in a computing device, the method comprising:
fetching an instruction of an instruction group for execution by a processor having an associated hardware resource;
applying a first hardware resource management policy to the fetched instruction of the instruction group to produce a first execution context, the first resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the given instruction group;
receiving a previously selected hardware resource management policy associated with the instruction, the previously selected hardware resource management policy having been selected based on at least one of theoretical information or historical information as being likely to provide a substantially optimum execution of the instruction group when the processor has a predefined execution context;
selecting a newly selected hardware resource management policy using one of the previously selected hardware resource management policy or the first hardware resource management policy in response to comparing the first and predefined execution contexts; and
applying the newly selected hardware resource management policy to the associated hardware resource if a predetermined similarity exists between the first execution context of the processor and the predefined execution context when the hardware resource management policy associated with the instruction was selected.
2. The method of claim 1, wherein the newly selected hardware resource management policy is stored for retrieval at a run time that is scheduled for the instruction of the instruction group.
3. The method of claim 1, wherein the optimistic policy assumes that less than a preselected level of at least one error will occur during execution of the instruction group.
4. The method of claim 1, further comprising:
facilitating execution of the instruction of an instruction group by the processor.
5. The method of claim 4, wherein the facilitating execution of the instruction of an instruction group by the processor further includes: at least one of initiate, activate, cause, accomplish, allow, andor achieve an execution of the instruction of an instruction group by the processor.
6. A computing device comprising:
means for receiving an instruction of an instruction group for execution by a processor having an associated hardware resource;
means for applying a first hardware resource management policy to the fetched instruction of the instruction group to produce a first execution context, the first resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the given instruction group;
means for receiving a previously selected hardware resource management policy associated with the instruction, the previously selected hardware resource management policy having been selected based on at least one of theoretical information or historical information as being likely to provide a substantially optimum execution of the instruction group when the processor has a predefined execution context;
means for selecting a newly selected hardware resource management policy using one of the previously selected hardware resource management policy or the first hardware resource management policy in response to comparing the first and predefined execution contexts; and
means for applying the newly selected resource management policy to the associated hardware resource if a predetermined similarity exists between the execution context of the processor and the predefined execution context existing when the selected resource management policy was selected, wherein at least one of the means is at least partially implemented using hardware.
7. The computing device of claim 6, further comprising: means for facilitating execution of the instruction of an instruction group by the processor.
8. The computing device of claim 6, wherein the means for receiving an instruction of an instruction group for execution by a processor having an associated hardware resource further includes: means for receiving an instruction of an instruction group for execution by a processor having an associated hardware resource, the associated hardware resource including at least one of a cache, a register, a functional unit, andor a branch predictor.
9. One or more non-transitory computer-readable media bearing program instructions that, when executed by a processing device, perform a process comprising:
applying an instruction of an instruction group for execution by a processor having an associated hardware resource;
applying a first hardware resource management policy to the fetched instruction of the instruction group to produce a first execution context, the first resource management policy being a pessimistic policy that assumes based on at least one of theoretical information or historical information that the given instruction group will execute in a substantially sub-optimal manner such that greater than a preselected level of at least one error will occur during execution of the given instruction group;
receiving a previously selected hardware resource management policy associated with the instruction, the previously selected hardware resource management policy having been selected based on at least one of theoretical information or historical information as being likely to provide a substantially optimum execution of the instruction group when the processor has a predefined execution context;
comparing the first execution context of the processor and the predefined execution context to determine if a predetermined correlation exists between the first execution context and the predefined execution context; and
applying the previously selected resource management policy to the associated hardware resource if the predetermined correlation exists between a present execution context of the processor and the predefined execution context.
10. The one or more non-transitory computer-readable media of claim 9, wherein the process further comprises:
facilitating execution of the instruction of an instruction group by the processor.