1. A method of testing a memory chip of a multi-chip memory package, comprising:
receiving a first external signal at a controller integrated on the memory chip to select the memory chip for testing;
activating a test mode of the controller in response to receiving the first external signal;
mapping external signal lines coupled to the controller to signal lines of the memory chip selected for testing in response to activating the test mode of the controller;
receiving a second external signal at controllers integrated on each of the remaining memory chips of the multi-chip memory package; and
at least restricting communication between external signal lines coupled to the controllers integrated on each of remaining memory chips and each of remaining memory chips in response to receiving the second external signal at the controllers integrated on each of the remaining memory chips.
2. The method of claim 1 further comprises deactivating the test mode of the controller integrated on the memory chip selected for testing to restore a relationship between the external signal lines and the signal lines of the memory chip selected for testing to that which occurs during normal operation of the multi-chip memory package in response to receiving a third external signal at the controller integrated on the memory chip selected for testing.
3. The method of claim 2 further comprises restoring a relationship between the external signal lines coupled to the controllers integrated on each of the remaining memory chips and each of the remaining memory chips to that which occurs during normal operation of the multi-chip memory package in response to receiving a fourth external signal at the controllers integrated on each of the remaining memory chips.
4. The method of claim 1, wherein operation of the controller during the test mode after the mapping differs from that which occurs during normal operation of that controller.
5. The method of claim 1, wherein each external signal line used during the test mode is also used to convey signals to andor from the controller during normal operation of that controller.
6. The method of claim 1, wherein at least restricting communication comprises preventing communication.
7. A method of testing a multi-chip memory package, comprising:
receiving an external signal at controllers integrated on each of a plurality of memory chips of the multi-chip memory package;
activating a first test mode of a controller of a memory chip in response to receiving the external signal at that controller;
mapping external signal lines coupled to the controller, whose first test mode is activated, to signal lines of the memory chip with that controller in response to activating the first test mode;
activating a second test mode of the controllers integrated on each of the remaining memory chips in response to receiving the external signal at those controllers; and
at least restricting communication between external signal lines coupled to the controllers integrated on each of remaining memory chips and each of remaining memory chips in response to activating the second test mode of the controllers integrated on each of the remaining memory chips.
8. The method of claim 7, wherein the external signal is a first external signal and further comprising receiving a second external signal at each of the controllers, wherein receiving the second external signal at the controller whose first test mode is activated deactivates the first test mode and receiving the second external signal at the controllers whose second test modes are activated deactivates the second test modes.
9. The method of claim 7, wherein the memory chip with the controller whose first test mode is activated has an address that matches an address included in the external signal.
10. The method of claim 9, wherein the memory chips with the controllers whose second test modes are activated have addresses that do not match the address included in the external signal.
11. A multi-chip integrated circuit package, comprising:
a plurality of integrated circuit devices; and
a controller integrated on each of the integrated circuit devices;
wherein each controller has first and second test modes;
wherein when the first test mode of a controller is activated that controller maps external signal lines coupled thereto to one or more signal lines of the integrated circuit device on which that controller is integrated; and
wherein when the second test mode of a controller is activated that controller at least restricts communication between the external signal lines and one or more signal lines of the integrated circuit device on which that controller is integrated.
12. The multi-chip integrated circuit package of claim 11, wherein the first and second test modes are activated in response to receiving at least one external signal at that controller.
13. The multi-chip integrated circuit package of claim 12, wherein the first test mode of an integrated circuit device is activated in response to that integrated circuit device receiving an external signal comprising an address that matches an address of that integrated circuit device.
14. The multi-chip integrated circuit package of claim 12, wherein the second test mode of an integrated circuit device is activated in response to that integrated circuit device receiving an external signal comprising an address that does not match that integrated circuit device.
15. The multi-chip integrated circuit package of claim 12, wherein the first test mode of an integrated circuit device is activated in response to the integrated circuit device receiving a first external signal and the second test mode of the integrated circuit device is activated in response to the integrated circuit device receiving a second external signal.
16. The multi-chip integrated circuit package of claim 12, wherein when the second test mode of a controller is activated that controller prevents communication between the external signal lines and one or more signal lines of the integrated circuit device on which that controller is integrated.
17. The multi-chip integrated circuit package of claim 12, wherein each external signal line used during the first test mode of a controller is also used to convey signals to andor from that controller during normal operation of that controller.
18. The multi-chip integrated circuit package of claim 11, wherein when the first test mode is activated for one of the memory chips, the second test mode is activated for the remaining memory chips.
19. A memory module, comprising:
one or more multi-chip memory packages, wherein at least one of the one or more multi-chip memory packages comprises:
a plurality of memory devices; and
a controller integrated on each of the memory devices;
wherein each controller has first and second test modes;
wherein when the first test mode of a controller is activated that controller maps external signal lines coupled thereto to one or more signal lines of the integrated circuit device on which that controller is integrated; and
wherein when the second test mode of a controller is activated that controller at least restricts communication between the external signal lines and one or more signal lines of the integrated circuit device on which that controller is integrated.
20. An electronic system, comprising:
a processor; and
at least one multi-chip memory package, the at least one multi-chip memory package, comprising:
a plurality of memory devices; and
a controller integrated on each of the memory devices and coupled to the processor by first signal lines;
wherein each controller has first and second test modes;
wherein when the first test mode of a controller is activated that controller maps at least a portion of the first signal lines to at least a portion of second signal lines of the integrated circuit device on which that controller is integrated; and
wherein when the second test mode of a controller is activated that controller at least restricts communication between at least a portion of the first signal lines and at least a portion of second signal lines of the integrated circuit device on which that controller is integrated.
21. The electronic system of claim 20, wherein the test modes are activated in response to receiving at least one signal at each controller from the processor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A connector, comprising:
a barrel;
an end bell having a spring arm and a seat portion;
an assembly nut having a projection disposed on the seat portion and engaging the spring arm to couple the barrel to the end bell; and
a securing mechanism securing the barrel and the assembly nut to each other.
2. The connector according to claim 1, wherein the securing mechanism includes a key formed on the barrel.
3. The connector according to claim 2, wherein the securing mechanism further includes a key groove formed along the assembly nut into which the key of the barrel is inserted.
4. The connector according to claim 3, wherein the securing mechanism further includes a C ring attached to the barrel.
5. The connector according to claim 1, wherein the end bell includes a nut receiving slot in which the projection is inserted.
6. The connector according to claim 5, wherein the nut receiving slot is positioned along an outer circumferential face of the end bell.
7. The connector according to claim 6, wherein the spring arm extends in a cantilever manner from the nut receiving slot.
8. The connector according to claim 7, wherein the seat portion extends from the outer circumferential face of the end bell.
9. The connector according to claim 8, wherein the seat portion is positioned below the spring arm and extends from a vicinity of the nut receiving slot.
10. The connector according to claim 9, wherein the seat portion is longer than the spring arm.
11. The connector according to claim 10, further comprising a stopper projection disposed along the outer circumferential face of the end bell and on the seat portion opposite to the nut receiving slot.
12. The connector according to claim 11, wherein the assembly nut includes a bottom plate and a side wall upstanding from an outer edge of the bottom plate.
13. The connector according to claim 12, wherein the projection is disposed along an upper end portion of the side wall.
14. The connector according to claim 13, wherein the seat portion includes a sloped portion extending from a thinner portion to a thicker portion thereof.
15. The connector according to claim 1, wherein the end bell includes a fitting portion with an approximately L-shaped receiving passageway extending there through.
16. The connector according to claim 15, wherein the approximately L-shaped receiving passageway includes a barrel receiving section and a cable receiving section positioned opposite the barrel receiving section.