1. A semiconductor device comprising:
a semiconductor substrate having an integrated circuit and an electrode that is connected electrically to the integrated circuit;
a resin layer formed on a surface of the semiconductor substrate on which the electrode is formed, avoiding the electrode; and
a wiring layer which is electrically connected to the electrode and has a land formed on the resin layer,
a penetrating hole that exposes the resin layer being formed in the land.
2. The semiconductor device as defined in claim 1,
the shape of the land in plan view being substantially circular.
3. The semiconductor device as defined in claim 1,
the penetrating hole being an elongated hole.
4. The semiconductor device as defined in claim 1,
the penetrating hole being an elongated hole extending along the outer edge portion of the land.
5. The semiconductor device as defined in claim 1,
a plurality of the penetrating holes being formed in the land.
6. The semiconductor device as defined in claim 5,
the penetrating holes being arranged along the outer edge portion of the land.
7. The semiconductor device as defined in claim 5,
the penetrating holes being disposed with substantially equal distances between adjacent holes.
8. The semiconductor device as defined in claim 1,
the land being formed on an upper surface of the resin layer.
9. The semiconductor device as defined in claim 1,
a plurality of the resin layers being formed at different positions in plan view on the semiconductor substrate; and
the land being formed integrally with an upper surface and a side surface of one of the resin layers.
10. The semiconductor device as defined in claim 9,
the penetrating hole being formed in a portion of the land covering the side surface of the resin layer.
11. The semiconductor device as defined in claim 9,
the side surface of the resin layer being tapered.
12. The semiconductor device as defined in claim 9,
the resin layer substantially having a shape of conical frustum.
13. The semiconductor device as defined in claim 1, further comprising:
a resist layer being formed on a surface of the semiconductor substrate on which the electrode is formed, and having an aperture that causes at least part of the land to be exposed.
14. The semiconductor device as defined in claim 13,
the shape of the aperture of the resist layer in plan view being substantially circular.
15. The semiconductor device as defined in claim 13,
the resist layer filling at least part of the penetrating hole.
16. The semiconductor device as defined in claim 13,
the resist layer being formed to fill the penetrating hole; and
part of an edge of the penetrating hole being substantially in contact with an edge of the aperture of the resist layer.
17. The semiconductor device as defined in claim 1, further comprising:
an external terminal provided on the land.
18. The semiconductor device as defined in claim 17, further comprising:
a second resin layer that avoids an upper portion of the external terminal but covers at least a lower portion of the external terminal.
19. The semiconductor device as defined in claim 1,
the semiconductor substrate being a semiconductor chip.
20. The semiconductor device as defined in claim 1,
the semiconductor substrate being a semiconductor wafer.
21. A circuit board on which is mounted the semiconductor device as defined in claim 1.
22. An electronic instrument comprising the semiconductor device as defined in claim 1.
23. A method of fabricating a semiconductor device, the method comprising:
forming a resin layer on a surface of a semiconductor substrate on which is formed an electrode that is connected electrically to an integrated circuit of the semiconductor substrate, avoiding the electrode; and
forming a wiring layer which is electrically connected to the electrode and has a land formed on the resin layer.
a penetrating hole that exposes the resin layer being formed in the land.
24. The method of fabricating a semiconductor device as defined in claim 23,
the penetrating hole being formed simultaneously with the wiring layer.
25. The method of fabricating a semiconductor device as defined in claim 23,
a plurality of the penetrating holes being formed in the land.
26. The method of fabricating a semiconductor device as defined in claim 23, further comprising:
forming a resist layer on a surface of the semiconductor substrate on which the electrode is formed, the resist layer having an aperture that causes at least part of the land to be exposed.
27. The method of fabricating a semiconductor device as defined in claim 23, further comprising:
forming an external terminal on the land.
28. The method of fabricating a semiconductor device as defined in claim 23, comprising:
forming a plurality of the resin layers at different positions in plan view on the semiconductor substrate;
providing a material of the wiring layer to cover at least the resin layer;
patterning a plated layer as a mask on the material of the wiring layer; and
forming the wiring layer and the penetrating hole by etching the material of the wiring layer and the plated layer in such a manner that portions of the material of the wiring layer covered by the plated layer remain.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed:
1. A multi-spectral product for use as target or identification and marking means, said product is configured as sandwiched structure suitable for simulating or marking of various objects, said sandwiched structure comprising a rear layer, carrying the structure,
a front layer, covered by two-dimensional pattern rendering the simulated object visually detectable and
an intermediate layer, overlapping with at least a portion of the front layer, said intermediate layer featuring thermal signature cue of the object,
wherein said front layer is made of a discontinuous material which enables detection of said thermal signature cue and its recognition in darkened conditions, while preserving possibility for recognizing the simulated object in visible light.
2. The product as defined in claim 1, in which said front layer is made of supple meshed fabric.
3. The product as defined in claim 2, in which said meshed fabric is made of knitted polyester.
4. The product as defined in claim 1, in which said net is made of high-density polyethylene.
5. The product, as defined in claim 1, in which said intermediate layer comprises low emissivity thermal coating.
6. The product, as defined in claim 5, in which said thermal coating is defined by heat reflection of about 0.7 and emissivity of about 0.3.
7. The product, as defined in claim 1, in which said layers are attached to each other in side-by-side relationship.
8. The product, as defined in claim 1, which is provided with fastening means suitable for securing thereof on a support structure.
9. The product as defined in claim 1, wherein said rear layer comprises lightweight polymeric material having sufficient strength to carry the structure and does not absorb water.
10. The product as defined in claim 1, which comprises a target means, suitable for simulating of various military or civilian objects.
11. The product as defined in claim 1, which comprises an identification and marking means.
12. The target device, as defined in claim 1, wherein said front intermediate and rear layers are made of polymeric material joined to form a unitary structure; said front layer comprising a polyester or polyethylene fabric with a plurality of substantially elliptically shaped holes;
said intermediate layer comprising a polyester sheet having at least one surface coated with a low emissivity thermal coating formed of a plurality of metallic layers interspersed with polyester; and
said rear layer comprising a strong, lightweight, polymeric material having sufficient strength to carry the superposed layers which also does not absorb water.
13. The target device, as defined in claim 10, wherein said intermediate layer comprises a plurality of aluminum layers, the emissivity of each layer being about 0.04-0.05, the top aluminum layer being coated with a low emissivity lacquer, the total thickness of said intermediate layer being about 24 microns.