1. A mask set configured to manufacture a pixel unit including a thin-film transistor (TFT) and a data line, comprising:
a first mask including an active layer pattern portion configured to form an active layer of the TFT;
a second mask including a gate electrode pattern portion configured to form a gate electrode of the TFT; and
a third mask including a source electrode pattern portion, a drain electrode pattern portion and a data line pattern portion respectively configured to form a source electrode and a drain electrode of the TFT and the data line, wherein
when the first mask, the second mask and the third mask are aligned and overlapped with each other, a maximum size value of an overlapped area between the active layer pattern portion of the first mask and the drain electrode pattern portion of the third mask in the direction parallel to the data line pattern portion is less than a size value of one side, overlapped with the data line pattern portion, in an overlapped area between the active layer pattern portion of the first mask and the source electrode pattern portion of the second mask.
2. The mask set according to claim 1, wherein the active layer pattern portion of the first mask is a first isosceles trapezoid; and
when the first mask, the second mask and the third mask are aligned and overlapped with each other, bases of the first isosceles trapezoid are disposed in the direction parallel to the data line pattern portion; an upper base of the first isosceles trapezoid is disposed in an overlapped area between the drain electrode pattern portion and the first isosceles trapezoid; and a lower base of the first isosceles trapezoid is disposed in an overlapped area between the source electrode pattern portion and the first isosceles trapezoid.
3. The mask set according to claim 2, wherein the gate electrode pattern portion of the second mask is a second isosceles trapezoid; and
when the first mask, the second mask and the third mask are aligned and overlapped, the second isosceles trapezoid completely covers the first isosceles trapezoid; bases of the second isosceles trapezoid are disposed in the direction parallel to the data line pattern portion; and the upper base of the second isosceles trapezoid and the upper base of the first isosceles trapezoid are disposed on a same side.
4. The mask set according to claim 2, wherein a sum of a size value of the upper base and the lower base of the first isosceles trapezoid is equal to twice a width value of the active layer pattern portion; and
the width value of the active layer pattern portion is a size value of one side of the active layer pattern portion parallel to the data line pattern portion where the active layer pattern portion is rectangular.
5. The mask set according to claim 1, wherein the second mask further includes a gate line pattern portion configured to form a gate line.
6. A method for manufacturing a pixel unit including a TEl and a data line, comprising:
adopting a second mask to form a gate electrode of the TFT on a substrate;
adopting a first mask to form an active layer of the TFT on the gate electrode: and
adopting a third mask to form a source electrode and a drain electrode of the TFT on the active layer and form the data line, so that a maximum size value of an overlapped area between the active layer and the drain electrode of the TFT in the direction parallel to the data line is less than a size value of one side, overlapped with the data line, in an overlapped area between the active layer and the source electrode of the TFT.
7. The method according to claim 6, before adopting the first mask to form the active layer of the TFT on the gate electrode, further comprising: forming a gate insulating layer covering the gate electrode.
8. A pixel unit, comprising a thin film transistor (TFT) and a data line, a source electrode of the TFT electrically connected with the data line, wherein
a maximum size value of an overlapped area between an active layer and a drain electrode of the TFT in the direction parallel to the data line is less than a size value of one side, overlapped with the data line, in an overlapped area between the active layer and the source electrode of the TFT; and
the source electrode is a portion of the data line disposed in an overlapped area between the active layer and the data line.
9. The pixel unit according to claim 8, wherein the active layer is a first isosceles trapezoid; bases of the first isosceles trapezoid are disposed in the direction parallel to the data line; an upper base of the first isosceles trapezoid is disposed in the overlapped area between the drain electrode and the active layer; and a lower base of the first isosceles trapezoid is disposed in an overlapped area between the source electrode and the active layer.
10. The pixel unit according to claim 9, wherein the gate electrode is a second isosceles trapezoid; the second isosceles trapezoid completely covers the first isosceles trapezoid; bases of the second isosceles trapezoid are disposed in the direction parallel to the data line; and an upper base of the second isosceles trapezoid and an upper base of the first isosceles trapezoid are disposed on a same side.
11. The pixel unit according to claim 9, wherein a sum of a size value of the upper base and the lower base of the first isosceles trapezoid is equal to twice a width value of the active layer; and
the width value of the active layer is the size value of one side of the active layer parallel to the data line when the active layer is rectangular.
12. The pixel unit according to claim 9, wherein a gate insulating layer configured to cover the gate electrode is disposed between the gate electrode and the active layer.
13. (canceled)
14. (canceled)
15. The mask set according to claim 3, wherein a sum of a size value of the upper base and the lower base of the first isosceles trapezoid is equal to twice a width value of the active layer pattern portion; and
the width value of the active layer pattern portion is a size value of one side of the active layer pattern portion parallel to the data line pattern portion where the active layer pattern portion is rectangular.
16. The pixel unit according to claim 10, wherein a sum of a size value of the upper base and the lower base of the first isosceles trapezoid is equal to twice a width value of the active layer; and
the width value of the active layer is the size value of one side of the active layer parallel to the data line when the active layer is rectangular.
17. The pixel unit according to claim 10, wherein a gate insulating layer configured to cover the gate electrode is disposed between the gate electrode and the active layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A detection method commonly used for a video interface outlet and earphone line outlet, comprising the following steps:
(1) allowing a detection device to detect whether a plug is inserted in a four-terminals outlet, if no, continuing detecting; otherwise, entering a next step;
(2) allowing said detection device to detect whether an impedance value of a video output terminal of said four-terminals outlet is larger than a preset value, if yes, causing said detection device to control said video output terminal to output a video signal; if no, causing said detection device to control said video signal output terminal not to output a video signal.
2. The method according to claim 1, wherein said detection device is connected to a plug detection terminal and video output terminal of said four-terminals outlet; said detection device emits a control signal to cause said video signal output terminal to output a video signal or not to output a video signal according to an output impedance value of said video output terminal when said detection device detects a message that a plug is inserted in said plug detection terminal.
3. The method according to claim 2, wherein said detection device comprises a microprocessor connected respectively to said plug detection terminal of said four-terminals outlet, control signal input terminals of first, second and third switch chips and a signal output terminal of a transistor; said first and second switch chips are further connected respectively to said transistor through corresponding resistors; a detection-use power supply input terminal is connected to said first switch chip; said power supply input terminal communicates said transistor and said second switch chip respectively through said corresponding resistors when said first switch chip is opened; said second switch chip is further connected to a video output terminal of said outlet; said microprocessor emits a signal to open respectively said first switch chip and said second chip respectively through said control signal input terminals when said microprocessor detects a message the a plug is inserted in said plug detection terminal; said detection-use power is caused to transmit to said transistor and said second switch chip, and said second switch chip is caused to rely on an output impedance value of said video output terminal to cause a signal output terminal of said transistor to feedback a level state of said output impedance to said microprocessor; said microprocessor then emits a control signal to said third switch chip to cause said third switch chip to control an amplifier to output a video signal or not to output a video signal to said video signal output terminal.
4. The method according to claim 3, wherein said microprocessor then emits a control signal to said third switch, and in the meantime, emits a control signal to close said first and second switch chips.
5. A detection device commonly used for a video interface outlet and earphone line outlet, comprising a detection device connected respectively to a plug detection terminal and video output terminal of a four-terminals outlet; thereby, said detection device can discern the type of an inserted plug according to an output impedance value of said video output terminal when said detection device detects a message that said plug is inserted in said plug detection terminal.
6. The device according to claim 5, wherein said detection device comprises a microprocessor connected respectively to said plug detection terminal of said four-terminals outlet, control signal input terminals of first and second switch chips and a signal output terminal of a transistor; said first and second switch chips are further connected respectively to said transistor through corresponding resistors; a detection-use power supply input terminal is connected to said first switch chip; said second switch chip is further connected to a video output terminal of said outlet; whereby said microprocessor emits a signal to open respectively said first switch chip and said second chip respectively through said control signal input terminals when said microprocessor detects a message that a plug is inserted in said plug detection terminal; said detection-use power is caused to transmit to said transistor and said second switch chip, and said second switch chip is caused to rely on an output impedance value of said video output terminal to cause a signal output terminal of said transistor to feedback a level state of said output impedance to said microprocessor so as to know the type of said inserted plug.
7. The device according to claim 6, wherein said microprocessor is further connected to a control signal input terminal of a third switch chip, said third switch chip is further connected to a power supply of a video signal amplifier so that said microprocessor emits a control signal to said third switch chip to cause said third switch chip to control said amplifier to output a video signal or not to output a video signal when said microprocessor detects a signal output terminal of said transistor is at a high voltage level or at a low voltage level.