1. A method, comprising:
receiving, by a wireless docking center device, at least from one or more wireless peripheral devices, capability-related information characterizing at least the one or more wireless peripheral devices;
receiving, by the wireless docking center device, from a wireless dockee device, or other capable device, planned use-related information of the wireless dockee device; and
analyzing, by the wireless docking center device, the received capability-related information and planned use-related information, and performing an action with respect to one or more wireless peripheral devices capable of performing at least a portion of services required by the planned use-related information of the wireless dockee device, based on the analysis.
2. The method of claim 1, further comprising:
providing, by the wireless docking center device, information resulting from the analysis, to at least one of the wireless dockee device for user notificationinformation of selected ones of the one or more wireless peripheral devices capable of performing services required by the planned use-related information of the wireless dockee device and to the one or more wireless peripheral devices, for automatically performing an action with respect to one or more of the wireless peripheral devices capable of performing services required by the planned use-related information of the wireless dockee device.
3. The method of claim 1, further comprising:
transmitting by the wireless docking center device, a status request to the one or more wireless peripheral devices, based on the planned use-related information of the wireless dockee device; and
receiving, by the wireless docking center device, from one or more wireless peripheral devices, in response to the status request, information characterizing the one or more wireless peripheral devices.
4. The method of claim 1, further comprising:
receiving, by the wireless docking center device, a request from the wireless dockee device for status of the one or more wireless peripheral devices; and
transmitting by the wireless docking center device to the wireless dockee device, information based on the information characterizing the one or more wireless peripheral devices specified in the request.
5. The method of claim 1, wherein the planned use-related information of the wireless dockee device is derived by the wireless dockee device from at least one of user settings and one or more applications or combinations of applications such as a calendar program in the dockee device, social networks or user activity related information.
6. The method of claim 1, wherein the planned use-related information of the wireless dockee device is derived by the wireless dockee device from sources including at least one of user settings and one or more applications or combinations of applications such as a calendar program in the wireless dockee device, social networks available to the wireless dockee device, user activity related information accumulated by the wireless dockee device, such as phone calls recently made or received using the wireless dockee device, or current location determined by a location determining unit in the wireless dockee device, and
wherein the wireless dockee device is programmed to select one or more of the sources or combinations of the sources to generate the planned use-related information.
7. The method of claim 1, wherein the wireless docking center device and the wireless dockee device are integrated.
8. An apparatus, comprising:
at least one processor;
at least one memory including computer program code;
the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to:
receive at least from one or more wireless peripheral devices, capability-related information characterizing at least the one or more wireless peripheral devices;
receive from a wireless dockee device, or other capable device, planned use-related information of the wireless dockee device; and
analyze the received capability-related information and planned use-related information, and perform an action with respect to one or more wireless peripheral devices capable of performing at least a portion of services required by the planned use-related information of the wireless dockee device, based on the analysis.
9. The apparatus of claim 8, further comprising:
the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to:
provide information resulting from the analysis, to at least one of the wireless dockee device for user notificationinformation of selected ones of the one or more wireless peripheral devices capable of performing services required by the planned use-related information of the wireless dockee device and to the one or more wireless peripheral devices, for automatically performing an action with respect to one or more of the wireless peripheral devices capable of performing services required by the planned use-related information of the wireless dockee device.
10. The apparatus of claim 8, further comprising:
the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to:
transmit a status request to the one or more wireless peripheral devices, based on the planned use-related information of the wireless dockee device; and
receive from one or more wireless peripheral devices, in response to the status request, information characterizing the one or more wireless peripheral devices.
11. The apparatus of claim 8, further comprising:
the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to:
receive a request from the wireless dockee device for status of the one or more wireless peripheral devices; and
transmit to the wireless dockee device, information based on the information characterizing the one or more wireless peripheral devices specified in the request.
12. The apparatus of claim 8, wherein the planned use-related information of the wireless dockee device is derived by the wireless dockee device from at least one of user settings and one or more applications or combinations of applications such as a calendar program in the dockee device, social networks or user activity related information.
13. The apparatus of claim 8, wherein the planned use-related information of the wireless dockee device is derived by the wireless dockee device from sources including at least one of user settings and one or more applications or combinations of applications such as a calendar program in the wireless dockee device, social networks available to the wireless dockee device, user activity related information accumulated by the wireless dockee device, such as phone calls recently made or received using the wireless dockee device, or current location determined by a location determining unit in the wireless dockee device, and
wherein the wireless dockee device is programmed to select one or more of the sources or combinations of the sources to generate the planned use-related information.
14. The apparatus of claim 8, wherein the apparatus and the wireless dockee device are integrated.
15. A computer program product comprising computer executable program code recorded on a computer readable, non-transitory storage medium, the computer executable program code, when executed by a computer processor, comprising:
code for receiving, by a wireless docking center device, at least from one or more wireless peripheral devices, capability-related information characterizing at least the one or more wireless peripheral devices;
code for receiving, by the wireless docking center device, from a wireless dockee device, or other capable device, planned use-related information of the wireless dockee device; and
code for analyzing, by the wireless docking center device, the received capability-related information and planned use-related information, and performing an action with respect to one or more wireless peripheral devices capable of performing at least a portion of services required by the planned use-related information of the wireless dockee device, based on the analysis.
16. The computer program product of claim 15, further comprising:
code for providing, by the wireless docking center device, information resulting from the analysis, to at least one of the wireless dockee device for user notificationinformation of selected ones of the one or more wireless peripheral devices capable of performing services required by the planned use-related information of the wireless dockee device and to the one or more wireless peripheral devices, for automatically performing an action with respect to one or more of the wireless peripheral devices capable of performing services required by the planned use-related information of the wireless dockee device.
17. The computer program product of claim 15, further comprising:
code for transmitting by the wireless docking center device, a status request to the one or more wireless peripheral devices, based on the planned use-related information of the wireless dockee device; and
code for receiving, by the wireless docking center device, from one or more wireless peripheral devices, in response to the status request, information characterizing the one or more wireless peripheral devices.
18. The computer program product of claim 15, further comprising:
code for receiving, by the wireless docking center device, a request from the wireless dockee device for status of the one or more wireless peripheral devices; and
code for transmitting by the wireless docking center device to the wireless dockee device, information based on the information characterizing the one or more wireless peripheral devices specified in the request.
19. The computer program product of claim 15, wherein the planned use-related information of the wireless dockee device is derived by the wireless dockee device from at least one of user settings and one or more applications or combinations of applications such as a calendar program in the dockee device, social networks or user activity related information.
20. The computer program product of claim 15, wherein the planned use-related information of the wireless dockee device is derived by the wireless dockee device from sources including at least one of user settings and one or more applications or combinations of applications such as a calendar program in the wireless dockee device, social networks available to the wireless dockee device, user activity related information accumulated by the wireless dockee device, such as phone calls recently made or received using the wireless dockee device, or current location determined by a location determining unit in the wireless dockee device, and
wherein the wireless dockee device is programmed to select one or more of the sources or combinations of the sources to generate the planned use-related information.
21. The computer program product of claim 15, wherein the wireless docking center device and the wireless dockee device are integrated.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An image sensor circuit comprising:
an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises:
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an autozeroing amplifier section having respective inputs coupled to the first and second input nodes and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a comparator section having respective inputs coupled to respective outputs of the autozeroing amplifier section, said comparator section capable of performing an offset reduction operation to compensate for offset between its inputs and capable of performing a decision operation using positive feedback to decide which of its inputs is being provided with a higher input voltage;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section,
wherein signals within an analog to digital converter are amplified by the autozeroing amplifier section before being supplied to the comparator section to reduce the effect of comparator section offset on comparator section decisions.
2. The image sensor circuit claimed in claim 1, further comprising a controller for supplying control signals to an analog to digital converter to cause the analog to digital converter to perform an offset reduction operation prior to analog to digital conversion of a pixel signal value.
3. The image sensor circuit claimed in claim 1, wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage.
4. The image sensor circuit claimed in claim 3, wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and respective first and second outputs of the autozeroing amplifier stage.
5. The image sensor circuit claimed in claim 4, further comprising a controller for supplying control signals to gates of said first and second reset transistors to perform an offset reduction operation by coupling said gates of the first and second input transistors and the respective first and second outputs of the autozeroing amplifier stage.
6. The image sensor circuit claimed in claim 3, wherein the autozeroing amplifier section comprises a plurality of cascaded autozeroing amplifier stages.
7. The image sensor circuit claimed in claim 1, wherein a respective analog to digital converter is provided for each of said columns of pixel circuits.
8. The image sensor circuit claimed in claim 1, wherein the first node is coupled to receive a pixel reset value as the reference value.
9. The image sensor circuit claimed in claim 1, wherein the first node is coupled to receive a reference pixel signal value as the reference value.
10. The image sensor circuit of claim 1,
wherein the comparator section is capable of performing a preset operation in which a potential from a voltage source is applied to output nodes of the comparator section.
11. The image sensor circuit of claim 1, wherein the comparator section comprises:
a first load transistor coupled between a voltage source and a first output node of the comparator section;
a second load transistor coupled between a voltage source and a second output node of the comparator section;
a first comparator enable transistor coupling the gate of the second load transistor to a first input transistor at a first input node of the comparator section; and
a second comparator enable transistor coupling the gate of the first load transistor to a second input transistor at a second input node of the comparator section.
12. An image sensor circuit comprising:
an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said signal pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises:
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an autozeroing amplifier section having respective inputs coupled to the first and second input nodes and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a comparator section having respective inputs coupled to respective outputs of the autozeroing amplifier section;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the autozeroing amplifier section before being supplied to the comparator section to reduce the effect of comparator section offset on comparator section decisions;
wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage;
wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and respective first and second inputs of the autozeroing amplifier stage; and
wherein each of said first and second input transistors is connected in series with a respective second transistor to form a cascode circuit.
13. An image sensor circuit comprising:
an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises:
a first input node for receiving a pixel reset value;
a second input node for receiving a pixel signal value;
an autozeroing comparator section having respective inputs coupled to the first input node and second input node and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the autozeroing comparator section;
wherein the autozeroing comparator section comprises:
a first input transistor for receiving a first input signal at its gate, and a second input transistor for receiving a second input signal at its gate;
a first reset transistor coupled between a gate of the first input transistor and a first output of the autozeroing comparator section, and a second reset transistor coupled between a gate of the second input transistor and a second output of the autozeroing comparator section;
a first load transistor coupled between the first output of the autozeroing comparator section and a voltage source node, and a second load transistor coupled between the second output of the autozeroing comparator section and the voltage source node;
a first autozero enable transistor coupled between a gate of the first load transistor and the first output of the comparator, and a second autozero enable transistor coupled between a gate of the second load transistor and the second output of the comparator;
a first comparator enable transistor coupled between the first output of the comparator and the gate of the second load transistor, and a second comparator enable transistor coupled between the second output of the comparator and the gate of the first load transistor;
a first preset transistor coupled between the first output of the comparator and the voltage source node, and a second preset transistor coupled between the second output of the comparator and the voltage source node; and
a first current enable transistor coupled in a path between the first input transistor and a ground node, and a second current enable transistor coupled in a path between the second input transistor and a ground node.
14. The image sensor circuit claimed in claim 13, further comprising a controller for supplying control signals to an analog to digital converter to cause the analog to digital converter to perform an offset reduction operation prior to analog to digital conversion of a pixel signal value.
15. The image sensor circuit claimed in claim 13, wherein the autozeroing comparator section is operable in a plurality of states including an offset reduction state, a preset state and a decision state.
16. The image sensor circuit claimed in claim 13, further comprising a controller for supplying respective control signals to gates of the first and second reset transistors, the first and second autozero enable transistors, the first and second comparator enable transistors, and the first and second current enable transistors to configure the autozeroing comparator section to operate in respective states including an offset reduction state, a preset state, and a decision state.
17. The image sensor circuit claimed in claim 13, further comprising a controller for supplying control signals to gates of said first and second reset transistors to perform an offset reduction operation by coupling said gates of the first and second input transistors to the respective first and second outputs of the autozeroing comparator section.
18. The image sensor circuit claimed in claim 13, wherein the autozeroing comparator section further comprises a buffer coupled to receive signals from said first and second nodes and coupled to supply said first input signal and second input signal to the gates of the first and second input transistors.
19. An image sensor circuit comprising:
an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises:
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section, said autozeroing comparator section capable of performing an offset reduction operation to compensate for offset between its inputs and capable of performing a decision operation using positive feedback to decide which of its inputs is being provided with a higher input voltage;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section,
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions.
20. The image sensor circuit claimed in claim 19, further comprising a controller for supplying control signals to an analog to digital converter to cause the analog to digital converter to perform an offset reduction operation prior to analog to digital conversion of a pixel signal value.
21. The image sensor circuit claimed in claim 19, wherein the amplifier section is an autozeroing amplifier section capable of performing an offset reduction operation to compensate for offset between its inputs.
22. The image sensor circuit claimed in claim 21, further comprising a controller for supplying respective control signals to the autozeroing amplifier section to configure the autozeroing amplifier to operate in respective states including an offset reduction state and an amplifying state, and for supplying respective control signals to configure the autozeroing comparator section to operate in respective states including an offset reduction state, a preset state, and a decision state.
23. The image sensor circuit claimed in claim 21, further comprising a controller for supplying control signals to the autozeroing amplifier section and the autozeroing comparator section to cause the autozeroing amplifier section and the autozeroing comparator section to perform respective offset reduction operations prior to analog to digital conversion of a pixel signal value.
24. The image sensor circuit claimed in claim 21, wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage.
25. The image sensor circuit claimed in claim 24, wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and the respective first and second outputs of the autozeroing amplifier stage.
26. The image sensor circuit claimed in claim 25, further comprising a controller for supplying control signals to gates of said first and second reset transistors to perform an offset reduction operation by coupling said gates of the first and second input transistors and respective first and second outputs of the autozeroing amplifier stage.
27. The image sensor circuit claimed in claim 24, wherein the autozeroing amplifier section comprises a plurality of cascaded autozeroing amplifier stages.
28. The image sensor circuit claimed in claim 19, wherein a respective analog to digital converter is provided for each of said columns of pixel circuits.
29. The image sensor circuit claimed in claim 19, wherein the first node is coupled to receive a pixel reset value as the reference value.
30. The image sensor circuit claimed in claim 19, wherein the first node is coupled to receive a reference pixel signal value as the reference value.
31. The image sensor circuit of claim 19,
wherein the autozeroing comparator section is capable of performing a preset operation in which a potential from a voltage source is applied to output nodes of the autozeroing comparator section.
32. The image sensor circuit of claim 19, wherein the autozeroing comparator section comprises:
a first load transistor coupled between a voltage source and a first output node of the autozeroing comparator section;
a second load transistor coupled between a voltage source and a second output node of the autozeroing comparator section;
a first comparator enable transistor coupling the gate of the second load transistor to a first input transistor at a first input node of the autozeroing comparator section; and
a second comparator enable transistor coupling the gate of the first load transistor to a second input transistor at a second input node of the autozeroing comparator section.
33. An image sensor circuit comprising:
an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises:
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions;
wherein the amplifier section is an autozeroing amplifier section capable of performing an offset reduction operation to compensate for offset between its inputs;
wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage;
wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and the respective first and second outputs of the autozeroing amplifier stage; and
wherein each of said first and second input transistors is connected in series with a respective second transistor to form a cascode circuit.
34. An image sensor circuit comprising:
an array of pixels comprised of rows and columns of pixel circuits;
a row driver for supplying respective control signals to rows of said pixel circuits; and
respective analog to digital converters connected to receive signals produced by columns of said pixel circuits;
wherein each of said analog to digital converters comprises:
a first input node for receiving a reference value;
a second input node for receiving a pixel signal value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input note; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions; and
wherein the autozeroing comparator section comprises:
a first input transistor for receiving a first input signal at its gate, and a second input transistor for receiving a second input signal at its gate;
a first reset transistor coupled between a gate of the first input transistor and a first output of the autozeroing comparator section, and a second reset transistor coupled between a gate of the second input transistor and a second output of the autozeroing comparator section;
a first load transistor coupled between the first output of the comparator and a voltage source node, and a second load transistor coupled between the second output of the comparator and the voltage source node;
a first autozero enable transistor coupled between a gate of the first load transistor and the first output of the comparator, and a second autozero enable transistor coupled between a gate of the second load transistor and the second output of the comparator;
a first comparator enable transistor coupled between the first output of the comparator and the gate of the second load transistor, and a second comparator enable transistor coupled between the second output of the comparator and the gate of the first load transistor;
a first preset transistor coupled between the first output of the comparator and the voltage source node, and a second preset transistor coupled between the second output of the comparator and the voltage source node; and
a first current enable transistor coupled in a path between the first input transistor and a ground node, and a second current enable transistor coupled in a path between the second input transistor and a ground node.
35. The image sensor circuit claimed in claim 34, further comprising a controller for supplying respective control signals to gates of the first and second reset transistors, the first and second autozero enable transistors, the first and second comparator enable transistors, and the first and second current enable transistors to configure the comparator section to operate in respective states including an offset reduction state, a preset state, and a decision state.
36. The image sensor circuit claimed in claim 34, further comprising a controller for supplying control signals to gates of said first and second reset transistors to perform an offset reduction operation by coupling said gates of the first and second input transistors to the respective first and second outputs of the autozeroing comparator section.
37. The image sensor circuit claimed in claim 34, wherein the autozeroing comparator section further comprises a buffer coupled to receive signals from said outputs of said amplifier section and coupled to supply said first input signal and second input signal to the gates of the first and second input transistors.
38. An analog to digital conversion circuit comprising:
a first input node for receiving a first value;
a second input node for receiving a second value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section, said autozeroing comparator section capable of performing an offset reduction operation to compensate for offset between its inputs and capable of performing a decision operation using positive feedback to decide which of its inputs is being provided with a higher input voltage;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section,
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions.
39. The circuit claimed in claim 38, further comprising a controller for supplying control signals to the analog to digital converter to cause the analog to digital converter to perform an offset reduction operation prior to performing an analog to digital conversion operation.
40. The circuit claimed in claim 38, wherein the amplifier section is an autozeroing amplifier section capable of performing an offset reduction operation to compensate for offset between its inputs.
41. The circuit claimed in claim 40, further comprising a controller for supplying respective control signals to the autozeroing amplifier section to configure the autozeroing amplifier to operate in respective states including an offset reduction state and an amplifying state, and for supplying respective control signals to configure the autozeroing comparator section to operate in respective states including an offset reduction state, a preset state, and a decision state.
42. The circuit claimed in claim 40, further comprising a controller for supplying control signals to the autozeroing amplifier section and the autozeroing comparator section to cause the autozeroing amplifier section and the autozeroing comparator section to perform respective offset reduction operations prior to performing an analog to digital conversion operation.
43. The circuit claimed in claim 40, wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage.
44. The circuit claimed in claim 43, wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second reset transistors coupled between the respective gates of the first and second input transistors and the respective first and second outputs of the autozeroing amplifier stage.
45. The circuit claimed in claim 44, further comprising a controller for supplying control signals to gates of said first and second reset transistors to perform an offset reduction operation by coupling said gates of the first and second input transistors and respective first and second outputs of the autozeroing amplifier stage.
46. The circuit claimed in claim 43, wherein the autozeroing amplifier section comprises a plurality of cascaded autozeroing amplifier stages.
47. The analog to digital conversion circuit of claim 38,
wherein the autozeroing comparator section is capable of performing a preset operation in which a potential from a voltage source is applied to output nodes of the autozeroing comparator section.
48. The analog to digital conversion circuit of claim 38, wherein the autozeroing comparator section comprises:
a first load transistor coupled between a voltage source and a first output node of the autozeroing comparator section;
a second load transistor coupled between a voltage source and a second output node of the autozeroing comparator section;
a first comparator enable transistor coupling the gate of the second load transistor to a first input transistor at a first input node of the autozeroing comparator section; and
a second comparator enable transistor coupling the gate of the first load transistor to a second input transistor at a second input node of the autozeroing comparator section.
49. An analog to digital conversion circuit comprising:
a first input node for receiving a first value;
a second input node for receiving a second value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing, an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions;
wherein the amplifier section is an autozeroing amplifier section capable of performing an offset reduction operation to compensate for offset between its inputs;
wherein the autozeroing amplifier section comprises at least one autozeroing amplifier stage;
wherein each of said at least one autozeroing amplifier stages comprises first and second input transistors for receiving respective input signals at their gates, and first and second rest transistors coupled between the respective gates of the first and second input transistors and the respective first and second outputs of the autozeroing amplifier stages; and
wherein each of said first and second input transistors is connected in series with a respective second transistor to form a cascode circuit.
50. An analog to digital conversion circuit comprising:
a first input node for receiving a first value;
a second input node for receiving a second value;
an amplifier section having respective inputs coupled to the first and second input nodes;
an autozeroing comparator section having respective inputs coupled to respective outputs of the amplifier section and being capable of performing an offset reduction operation to compensate for offset between its inputs;
a group of binary scaled capacitors having respective first nodes coupled to the second input node; and
a set of conversion latches connected to respective second nodes of the binary scaled capacitors, the set of conversion latches coupled to receive an output of the autozeroing comparator section and comprising a logic circuit for selectively applying voltages to respective second nodes of the binary scaled capacitors in response to output values received from the comparator section;
wherein signals within an analog to digital converter are amplified by the amplifier section before being supplied to the autozeroing comparator section to reduce the effect of comparator section offset on comparator section decisions; and
wherein the autozeroing comparator section comprises:
a first input transistor for receiving a first input signal at its gate, and a second input transistor for receiving a second input signal at its gate;
a first reset transistor coupled between a gate of the first input transistor and a first output of the autozeroing comparator section, and a second reset transistor coupled between a gate of the second input transistor and a second output of the autozeroing comparator section;
a first load transistor coupled between the first output of the comparator and a voltage source node, and a second load transistor coupled between the second output of the comparator and the voltage source node;
a first autozero enable transistor coupled between a gate of the first load transistor and the first output of the comparator, and a second autozero enable transistor coupled between a gate of the second load transistor and the second output of the comparator;
a first comparator enable transistor coupled between the first output of the comparator and the gate of the second load transistor, and a second comparator enable transistor coupled between the second output of the comparator and the gate of the first load transistor;
a first preset transistor coupled between the first output of the comparator and the voltage source node, and a second preset transistor coupled between the second output of the comparator and the voltage source node; and
a first current enable transistor coupled in a path between the first input transistor and a ground node, and a second current enable transistor coupled in a path between the second input transistor and a ground node.
51. The circuit claimed in claim 50, further comprising a controller for supplying respective control signals to gates of the first and second reset transistors, the first and second autozero enable transistors, the first and second comparator enable transistors, and the first and second current enable transistors to configure the comparator section to operate in respective states including an offset reduction state, a preset state, and a decision state.
52. The circuit claimed in claim 50, further comprising a controller for supplying control signals to gates of said first and second reset transistors to perform an offset reduction operation by coupling said gates of the first and second input transistors to the respective first and second outputs of the autozeroing comparator section.
53. The circuit claimed in claim 50, wherein the autozeroing comparator section further comprises a buffer coupled to receive signals from said outputs of said amplifier section and coupled to supply said first input signal and second input signal to the gates of the first and second input transistors.
54. A method in an analog to digital converter comprising:
connecting respective inputs of a comparator of the analog to digital converter to corresponding outputs of the analog to digital converter to store offset compensation values in respective capacitors coupled to the respective inputs of the comparator;
contemporaneously with connecting the inputs of the comparator to the corresponding outputs of the comparator, connecting respective inputs of an amplifier of the analog to digital converter to corresponding outputs of the amplifier;
disconnecting the inputs of the amplifier from the corresponding outputs of the amplifier;
disconnecting the inputs of the comparator from the corresponding outputs of the comparator after disconnecting the inputs of the amplifier from the corresponding outputs of the amplifier; and
providing a series of one or more signals at the respective inputs of the comparator to produce a series of output decisions by the comparator,
wherein said series of one or more signals provided at the respective inputs of the comparator are provided through said amplifier.