1-15. (canceled)
16. An apparatus, comprising:
a comparator configured to identify
features of a first image, and
features of a second image that match the features of the first image; and
a stabilizer configured to stabilize a motion of one of the first and second images
if a distribution of the features of the first image meets a first criterion, and
if a distribution of the features of the second image meets a second criterion.
17. The apparatus of claim 16 wherein:
the distribution of the features of the first image includes a spatial distribution; and
the distribution of the features of the second image includes a spatial distribution.
18. The apparatus of claim 16 wherein the first criterion equals the second criterion.
19. The apparatus of claim 16 wherein one of the first and second criteria includes that one of the features is located near a first corner of a respective one of the first and second images and that another of the features is located near a second corner of the respective one of the first and second images, the second corner being diagonally opposite to the first corner.
20. The apparatus of claim 16 wherein one of the first and second criteria includes that one of the features is located near a first side of a respective one of the first and second images and that another of the features is located near a second side of the respective one of the first and second images, the second side being opposite to the first side.
21. The apparatus of claim 16 wherein one of the first and second criteria includes that one of the features is located near a corner of a respective one of the first and second images and that another of the features is located near a side of the respective one of the first and second images, the side being opposite from the corner.
22. The apparatus of claim 16 wherein one of the first and second criteria includes that one of the features is located near a first corner of a respective one of the first and second images, that another of the features is located near a first side of the respective one of the first and second images, and that yet another of the features is located near a second side of the respective one of the first and second images, the first and second sides forming a second corner of the respective one of the first and second images, the second corner being opposite the first corner.
23. The apparatus of claim 16 wherein one of the first and second criteria includes that one of the features is located near a first corner of a respective one of the first and second images, another one of the features is located near a second corner of the respective one of the first and second images, yet another one of the features is located near a third corner of the respective one of the first and second images, and still another one of the features is located near a fourth corner of the respective one of the first and second images.
24. The apparatus of claim 16, further comprising an outlier remover configured:
to identify as an outlier feature any outlying feature of the first and second images identified by the comparator;
to identify as an inlier feature any other feature of the first and second images identified by the comparator; and
to provide the inlier features to the stabilizer.
25. The apparatus of claim 16, further comprising a filter configured to filter the features of the first and second images identified by the comparator, and to provide the filtered features to the stabilizer, if the distribution of the features of the first image meets the first criterion and the distribution of the features of the second image meets the second criterion.
26. The apparatus of claim 16, further comprising:
a first outlier remover configured,
to identify as a first outlier feature any outlying feature of the first and second images identified by the comparator,
to identify as an inlier feature any other feature of the first and second images identified by the comparator;
a distribution detector configured
to determine if the distribution of the inlier features of the first image meets the first criterion,
to determine if the distribution of the inlier features of the second image meets the second criterion,
to provide the inlier features of the first and second images to the stabilizer if the distribution of the features of the first image meets the first criterion and the distribution of the features of the second image meets the second criterion,
to provide the first outlier features to a second outlier remover if a number of the first outlier features is greater than a threshold, and the distribution of the features of the first image does not meet the first criterion or the distribution of the features of the second image does not meet the second criterion, and
to bypass the stabilizer if the number of first outlier features is less than the threshold, and the distribution of the features of the first image does not meet the first criterion or the distribution of the features of the second image does not meet the second criterion; and
the second outlier remover is configured
to identify as a second outlier feature any outlying first outlier feature of the first and second images, and
to provide to the distribution detector as a respective inlier feature each of the second outlier features.
27. A system, comprising:
a first integrated circuit including
a comparator configured to identify
features of a first image, and
features of a second image that match the features of the first image, and
a stabilizer configured to stabilize a motion of one of the first and second images
if a distribution of the features of the first image meets a first criterion, and
if a distribution of the features of the second image meets a second criterion; and
a second integrated circuit coupled to the first integrated circuit.
28. The system of claim 27 wherein the first and second integrated circuits are disposed on a same die.
29. The system of claim 27 wherein the first and second integrated circuits are disposed on respective dies.
30. The system of claim 27 wherein one of the first and second integrated circuits includes a computing circuit.
31. A method, comprising:
identifying features of a first image;
identifying features of a second image that match the features of the first image; and
stabilizing a motion of one of the first and second images
if a distribution of the identified features of the first image meets a first criterion, and if a distribution of the identified features of the second image meets a second criterion.
32. The method of claim 31, further comprising extracting the features of the first and second images before identifying the features.
33. The method of claim 31 wherein the first criterion equals the second criterion.
34. The method of claim 31 wherein one of the first and second criteria includes that one of the features is located near a first corner of a respective one of the first and second images and that another of the features is located near a second corner of the respective one of the first and second images, the second corner being diagonally opposite to the first corner.
35. The method of claim 31 wherein one of the first and second criteria includes that one of the features is located near a first side of a respective one of the first and second images and that another of the features is located near a second side of the respective one of the first and second images, the second side being opposite to the first side.
36. The method of claim 31 wherein one of the first and second criteria includes that one of the features is located near a corner of a respective one of the first and second images and that another of the features is located near a side of the respective one of the first and second images, the side being opposite from the corner.
37. The method of claim 31, further comprising:
identifying as an outlier feature any outlying ones of the identified features of the first and second images;
identifying as an inlier feature any other ones of the identified features of the first and second images; and
wherein stabilizing includes stabilizing the motion of one of the first and second images if a distribution of the inlier features of the first image meets a first criterion, and if a distribution of the inlier features of the second image meets a second criterion.
38. The method of claim 31, further comprising:
filtering the identified features of the first and second images identified by the comparator, and
wherein stabilizing includes stabilizing the motion of one of the first and second images if a distribution of the filtered features of the first image meets a first criterion, and if a distribution of the filtered features of the second image meets a second criterion.
39. A non-transitory computer-readable medium storing program instructions, that, when executed by one or more computing circuits, cause the one or more computing circuits, or cause an apparatus under control of the one or more computing circuits:
to identify features of a first image;
to identify features of a second image that match the features of the first image; and
to stabilize a motion of one of the first and second images
if a distribution of the identified features of the first image meets a first criterion, and if a distribution of the identified features of the second image meets a second criterion.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor integrated circuit made up by integrating a plurality of first conduction type MOS transistors with a plurality of second conduction type MOS transistors, said semiconductor integrated circuit comprising:
a first power supply line for supplying a first power source voltage;
a first MOS transistor of the plurality of the first conduction type MOS transistors, having a first threshold voltage, provided with a gate electrode, a first electrode, and a second electrode, the first electrode being connected to the first power supply line;
a first pseudo power supply line connected to the second electrode of the first MOS transistor;
an internal logic circuit comprising at least a second MOS transistor of the plurality of the first conduction type MOS transistors, having a second threshold voltage lower than the first threshold voltage, supplied with the first power source voltage via the first pseudo power supply line; and
a first terminal for supplying a suitable voltage to a substrate terminal of the second MOS transistor.
2. A semiconductor integrated circuit according to claim 1, wherein the first power source voltage is applied to a substrate terminal of the first MOS transistor.
3. A semiconductor integrated circuit according to claim 1, wherein the first terminal is connected to a substrate terminal of the first MOS transistor.
4. A semiconductor integrated circuit according to claim 1, further comprising:
a second power supply line for supplying a second power source voltage, different from the first power source voltage;
a third MOS transistor of the plurality of the second conduction type MOS transistors, having a third threshold voltage, provided with a gate electrode, a first electrode, and a second electrode, the first electrode being connected to the second power supply line; and
a second pseudo power supply line connected to the second electrode of the third MOS transistor, for supplying the second power source voltage to the internal logic circuit, said internal logic circuit comprising at least a fourth MOS transistor of the plurality of the second conduction type MOS transistors, having a fourth threshold voltage lower than the third threshold voltage,
said semiconductor integrated circuit still further comprising a second terminal for supplying a suitable voltage to a substrate terminal of the fourth MOS transistor.
5. A semiconductor integrated circuit according to claim 4, wherein the second power source voltage is applied to a substrate terminal of the third MOS transistor.
6. A semiconductor integrated circuit according to claim 4, wherein the second terminal is connected to a substrate terminal of the third MOS transistor.
7. A semiconductor integrated circuit according to claim 1, further comprising a third terminal connected to the first power supply line, said third terminal being connected to the first terminal by means of wire bonding.
8. A semiconductor integrated circuit according to claim 4, further comprising a fourth terminal connected to the second power supply line, said fourth terminal being connected to the second terminal by means of wire bonding.
9. A semiconductor integrated circuit according to claim 1, further comprising a voltage generation circuit for supplying a substrate terminal of the first MOS transistor with a predetermined voltage according to a test signal inputted via the first terminal.
10. A semiconductor integrated circuit according to claim 4, further comprising a voltage generation circuit for supplying a substrate terminal of the first and the third MOS transistors, respectively, with a predetermined voltage according to a test signal inputted via the first terminal or the second terminal.
11. A method of testing a semiconductor integrated circuit, using the semiconductor integrated circuit as set forth in claim 1, wherein the first MOS transistor is turned into a conducting state by supplying the first power supply line with the first power source voltage, and a voltage so as to increase a threshold voltage of the second MOS transistor is supplied to the substrate terminal of the second MOS transistor by use of the first terminal before measuring a value of current flowing through the internal logic circuit.
12. A method of testing a semiconductor integrated circuit, using the semiconductor integrated circuit as set forth in claim 4, wherein the first and third MOS transistors are turned into a conducting state by supplying the first power supply line with the first power source voltage and supplying the second power supply line with the second power source voltage, respectively, and a voltage so as to increase a threshold voltage of the second MOS transistor is supplied to the substrate terminal of the second MOS transistor by use of the first terminal while a voltage so as to increase a threshold voltage of the fourth MOS transistor is supplied to the substrate terminal of the fourth MOS transistor by use of the second terminal before measuring a value of current flowing through the internal logic circuit.
13. A semiconductor integrated circuit according to claim 3, wherein the first and second MOS transistors are formed in a first well layer of the second conduction type, formed in a semiconductor substrate, the first terminal being connected to the first well. cm 14. A semiconductor integrated circuit according to claim 2, wherein the first MOS transistor is formed in a first well layer of the second conduction type, formed in a second conduction type semiconductor substrate while the second MOS transistor is formed in a third well layer of the second conduction type, within a second well layer of the first conduction type, formed in the second conduction type semiconductor substrate, the first terminal being connected to the third well layer.