1. A method for measuring a capacitance associated with a portion of an integrated circuit comprising:
coupling a measurement circuit to an integrated circuit;
initializing one or more transistors within the integrated circuit;
measuring a capacitance associated with a portion of the integrated circuit using the measurement circuit, the portion of the integrated circuit being selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement; and
separating the capacitance measurement associated with the portion of the integrated circuit into a capacitance associated with the transistors included within the integrated circuit and a capacitance associated with one or more interconnects that are coupled to the transistors.
2. The method of claim 1, wherein the portion of the integrated circuit defines a static random access memory (SRAM) element.
3. The method of claim 2, further comprising:
duplicating the SRAM element multiple times before executing the capacitance measurement associated with the portion of the integrated circuit.
4. The method of claim 1, further comprising:
comparing the capacitance measurement associated with the portion of the integrated circuit to a reference set of capacitance values such that a parameter associated with the manufacturing process that generated the integrated circuit may be checked.
5. The method of claim 4, wherein the parameter associated with the manufacturing process is selected from the group consisting of:
(a) specifications associated with the transistor;
(b) a width of a selected one of the conductors;
(c) a thickness of a selected one of the conductors;
(d) a thickness associated with a dielectric positioned proximate to a selected two or more of the conductors; and
(e) a spacing between a selected two or more of the conductors.
6. The method of claim 5, wherein the reference set of capacitance values is based on a simulation element having substantially the same structural characteristics as the integrated circuit.
7. The method of claim 5, wherein the manufacturing process that generated the integrated circuit is changed in response to comparing the capacitance measurement associated with the portion of the integrated circuit to the reference set of capacitance values.
8. An apparatus for measuring a capacitance associated with a portion of an integrated circuit comprising:
an integrated circuit that includes one or more transistors;
a measurement circuit coupled to the integrated circuit and operable to initialize one or more of the transistors within the integrated circuit such that a steady-state associated with one or more of the transistors is achieved, wherein the measurement circuit is used to measure a capacitance associated with a portion of the integrated circuit, the portion of the integrated circuit being selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement; and
wherein the capacitance measurement associated with the portion of the integrated circuit is separated into a capacitance associated with the transistors included within the integrated circuit and a capacitance associated with one or more interconnects that are coupled to the transistors.
9. The apparatus of claim 8, wherein the portion of the integrated circuit defines a static random access memory (SRAM) element.
10. The apparatus of claim 9, wherein the SRAM element is duplicated multiple times before executing the capacitance measurement associated with the portion of the integrated circuit.
11. The apparatus of claim 8, further comprising:
a reference set of capacitance values, wherein the capacitance measurement associated with the portion of the integrated circuit may be compared to the reference set of capacitance values such that a parameter associated with the manufacturing process that generated the integrated circuit may be checked.
12. The apparatus of claim 11, wherein the parameter associated with the manufacturing process is selected from the group consisting of:
(a) specifications associated with the transistor;
(b) a width of a selected one of the conductors;
(c) a thickness of a selected one of the conductors;
(d) a thickness associated with a dielectric positioned proximate to a selected two or more of the conductors; and
(e) a spacing between a selected two or more of the conductors.
13. The apparatus of claim 12, wherein the reference set of capacitance values is based on a simulation element having substantially the same structural characteristics as the integrated circuit.
14. The apparatus of claim 12, wherein the manufacturing process that generated the integrated circuit is changed in response to comparing the capacitance measurement associated with the portion of the integrated circuit to the reference set of capacitance values.
15. A system for measuring a capacitance associated with a portion of an integrated circuit comprising:
a measurement circuit operable to initialize one or more transistors within an integrated circuit such that a steady-state associated with one or more of the transistors is achieved, wherein the measurement circuit is coupled to the integrated circuit which is selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement; and
wherein the capacitance measurement associated with the portion of the integrated circuit is separated into a capacitance associated with the transistors included within the integrated circuit and a capacitance associated with one or more interconnects that are coupled to the transistors.
16. The system of claim 15, wherein the portion of the integrated circuit defines a static random access memory (SRAM) element.
17. The system of claim 16, wherein the SRAM element is duplicated multiple times before executing the capacitance measurement associated with the portion of the integrated circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for forming a multi-layer shallow trench isolation structure in a semiconductor device, the method comprising the steps of:
etching a shallow trench in a silicon substrate of a semiconductor device;
forming a dielectric liner layer on a floor and walls of the shallow trench;
forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen, and sources of doping materials at a first processing condition; and
forming a second doped oxide layer above and in direct contact with the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition, different from the first processing condition; wherein
the doping materials in the first doped oxide layer comprise boron and phosphorus; and
the first processing condition comprises boron concentration in the range of approximately 4-8 wt %, phosphorus concentration in the range of approximately 3-6 wt %.
2. The method of claim 1, wherein:
the dielectric liner layer comprises a silicon oxide layer and a Nitrogen containing layer.
3. The method of claim 1, wherein:
the doping materials in the second doped oxide layer are boron and phosphorus;
the second processing condition comprises boron concentration in the range of approximately 4-6 wt %, phosphorus concentration in the range of approximately 4-6 wt %.
4. The method of claim 1, further comprising depositing a cap oxide layer above the second doped oxide layer, keeping a thickness ratio between the second doped oxide layer and the cap oxide layer in the range of approximately 1 to 6.
5. The method of claim 1, wherein a thickness ratio between the first doped oxide layer and the second doped oxide layer is in the range of approximately 0.1 to 1.
6. A method for forming a multi-layer shallow trench isolation structure in a semiconductor device, the method comprising the steps of:
etching a shallow trench in a silicon substrate of a semiconductor device;
forming a dielectric liner layer on a floor and walls of the shallow trench;
forming a doped oxide layer above the dielectric liner layer by vapor deposition using precursors of silicon and doping materials; and
forming a silicon oxide layer above the doped oxide layer by atomic layer deposition;
wherein:
a thickness ratio of the doped oxide layer to the silicon oxide layer is in the range of approximately 0.1 to 1;
the doping materials in the first doped oxide layer comprise boron and phosphorus; and
doping components of the doped oxide layer comprise boron concentration in the range of approximately 4-8 wt %, phosphorus concentration in the range of approximately 3-6 wt %.
7. The method of claim 6, wherein:
the dielectric liner layer comprises a silicon oxide layer and a Nitrogen containing layer.
8. The method of claim 6, further comprising depositing a cap oxide layer above the silicon oxide layer, keeping a thickness ratio between the silicon oxide layer and the cap oxide layer in the range of approximately 1 to 6.