1. A memory hub, comprising:
a first plurality of bit-lane terminals;
a second plurality of bit-lane terminals;
at least one memory device interface; and
a switch coupled to the bit-lane terminals in the first and second plurality and to the at least one memory device interface, the switch including a switching circuit that is operable to couple at least some of the bit-lane terminals in the first plurality to either a respective one of the bit-lane terminals in the second plurality or at least one other bit-lane terminal in the second plurality, the switching circuit further being operable to couple at least some of the bit-lane terminals in the first plurality to the at least one memory device interface.
2. The memory hub of claim 1 wherein the switching circuit is further operable to couple at least some of the bit-lane terminals in the second plurality to the at least one memory device interface.
3. The memory hub of claim 1 wherein the at least one other bit-lane terminal in the second plurality to which the switch is operable to couple at least some of the bit-lane terminals in the first plurality comprises a respective bit-lane terminal in the second plurality that is adjacent the bit-lane terminal in the first second plurality that corresponds to the respective bit-lane terminal in the first plurality.
4. The memory hub of claim 1 wherein the bit-lane terminals in the first plurality comprise respective bi-directional bit-lane terminals.
5. The memory hub of claim 4 wherein the bit-lane terminals in the second plurality comprise respective bi-directional bit-lane terminals.
6. The memory hub of claim 1 wherein the bit-lane terminals in the first plurality comprise in number four bit-lane terminals.
7. A memory module, comprising:
a substrate having a first connector and a second connector;
a plurality of memory devices mounted on the substrate;
a memory hub mounted on the substrate and coupled to the plurality of memory devices, the memory hub comprising:
a first plurality of bit-lane terminals connected to the first connector;
a second plurality of bit-lane terminals connected to the second connector;
at least one memory device interface; and
a switch coupled to the bit-lane terminals in the first and second plurality and to the at least one memory device interface, the switch including a switching circuit that is operable to couple at least some of the bit-lane terminals in the first plurality to either a respective one of the bit-lane terminals in the second plurality or at least one other bit-lane terminal in the second plurality, the switching circuit further being operable to couple at least some of the bit-lane terminals in the first plurality to the at least one memory device interface.
8. The memory module of claim 7 wherein the switching circuit is further operable to couple at least some of the bit-lane terminals in the second plurality to the at least one memory device interface.
9. The memory module of claim 7 wherein the at least one other bit-lane terminal in the second plurality to which the switch is operable to couple at least some of the bit-lane terminals in the first plurality comprises a respective bit-lane terminal in the second plurality that is adjacent the bit-lane terminal in the first second plurality that corresponds to the respective bit-lane terminal in the first plurality.
10. The memory module of claim 7 wherein the bit-lane terminals in the first plurality comprise respective bi-directional bit-lane terminals.
11. The memory module of claim 10 wherein the bit-lane terminals in the second plurality comprise respective bi-directional bit-lane terminals.
12. The memory module of claim 7 wherein the bit-lane terminals in the first plurality comprise in number four bit-lane terminals.
13. The memory module of claim 7 wherein the memory devices comprise dynamic random access memory devices.
14. A memory system, comprising:
a plurality of memory modules, each of the memory modules comprising:
a substrate having a first connector and a second connector;
a plurality of memory devices mounted on the substrate;
a memory hub mounted on the substrate and coupled to the plurality of memory devices, the memory hub comprising:
a first plurality of bit-lane terminals;
a second plurality of bit-lane terminals;
at least one memory device interface; and
a switch coupled to the bit-lane terminals in the first and second plurality and to the at least one memory device interface, the switch including a switching circuit that is operable to couple at least some of the bit-lane terminals in the first plurality to either a respective one of the bit-lane terminals in the second plurality or at least one other bit-lane terminal in the second plurality, the switching circuit further being operable to couple at least some of the bit-lane terminals in the first plurality to the at least one memory device interface;
a memory hub controller having a plurality of bit-lane terminals; and
a plurality of bit-lanes connecting the bit-lane terminals of the memory hub controller to the bit-lanes in the first plurality of bit-lanes of the memory hub in one of the memory modules, the first plurality of bit-lane terminals of the memory hubs in the other memory modules being connected by respective bit-lanes to respective bit-lane terminals in the second plurality of bit-lanes terminals of the memory hub in another of the memory modules.
15. The memory system of claim 14 wherein the switching circuit is further operable to couple at least some of the bit-lane terminals in the second plurality to the at least one memory device interface.
16. The memory system of claim 14 wherein the at least one other bit-lane terminal in the second plurality to which the switch is operable to couple at least some of the bit-lane terminals in the first plurality comprises a respective bit-lane terminal in the second plurality that is adjacent the bit-lane terminal in the first second plurality that corresponds to the respective bit-lane terminal in the first plurality.
17. The memory system of claim 14 wherein the bit-lane terminals in the first plurality comprise respective bi-directional bit-lane terminals.
18. The memory system of claim 17 wherein the bit-lane terminals in the second plurality comprise respective bi-directional bit-lane terminals.
19. The memory system of claim 14 wherein the bit-lane terminals in the first plurality comprise in number four bit-lane terminals.
20. The memory system of claim 14 wherein the memory devices comprise dynamic random access memory devices.
21. The memory system of claim 14 wherein the switching circuit in the memory hub in each of the memory modules is operable to couple the bit-lane terminals in the first plurality to respective bit-lane terminals in the second plurality that correspond to the respective bit lane terminals of the first plurality in the memory hub controller to which the respective bit-lane terminals in the first plurality are coupled as long as the bit-lanes connecting the respective bit-lane terminals in the second plurality to respective bit-lane terminals in the first plurality in the memory hub in another memory module are operable.
22. A processor-based system, comprising:
a processing unit operable to perform computing functions;
a system controller coupled to the processing unit;
at least one input device coupled to the processing unit through the system controller;
at least one output device coupled to the processing unit through the system controller;
at least one data storage devices coupled to the processing unit through the system controller;
a plurality of memory modules, each of the memory modules comprising:
a substrate having a first connector and a second connector;
a plurality of memory devices mounted on the substrate;
a memory hub mounted on the substrate and coupled to the plurality of memory devices, the memory hub comprising:
a first plurality of bit-lane terminals;
a second plurality of bit-lane terminals;
at least one memory device interface; and
a switch coupled to the bit-lane terminals in the first and second plurality and to the at least one memory device interface, the switch including a switching circuit that is operable to couple at least some of the bit-lane terminals in the first plurality to either a respective one of the bit-lane terminals in the second plurality or at least one other bit-lane terminal in the second plurality, the switching circuit further being operable to couple at least some of the bit-lane terminals in the first plurality to the at least one memory device interface;
a memory hub controller having a plurality of bit-lane terminals, the memory hub controller being coupled to the processing unit through the system controller; and
a plurality of bit-lanes connecting the bit-lane terminals of the memory hub controller to the bit-lanes in the first plurality of bit-lanes of the memory hub in one of the memory modules, the first plurality of bit-lane terminals of the memory hubs in the other memory modules being connected by respective bit-lanes to respective bit-lane terminals in the second plurality of bit-lanes terminals of the memory hub in another of the memory modules.
23. The processor-based system of claim 22 wherein the switching circuit is further operable to couple at least some of the bit-lane terminals in the second plurality to the at least one memory device interface.
24. The processor-based system of claim 22 wherein the at least one other bit-lane terminal in the second plurality to which the switch is operable to couple at least some of the bit-lane terminals in the first plurality comprises a respective bit-lane terminal in the second plurality that is adjacent the bit-lane terminal in the first second plurality that corresponds to the respective bit-lane terminal in the first plurality.
25. The processor-based system of claim 22 wherein the bit-lane terminals in the first plurality comprise respective bi-directional bit-lane terminals.
26. The processor-based system of claim 25 wherein the bit-lane terminals in the second plurality comprise respective bi-directional bit-lane terminals.
27. The processor-based system of claim 22 wherein the bit-lane terminals in the first plurality comprise in number four bit-lane terminals.
28. The processor-based system of claim 22 wherein the memory devices comprise dynamic random access memory devices.
29. The processor-based system of claim 22 wherein the switching circuit in the memory hub in each of the memory modules is operable to couple the bit-lane terminals in the first plurality to respective bit-lane terminals in the second plurality that correspond to the respective bit lane terminals of the first plurality in the memory hub controller to which the respective bit-lane terminals in the first plurality are coupled as long as the bit-lanes connecting the respective bit-lane terminals in the second plurality to respective bit-lane terminals in the first plurality in the memory hub in another memory module are operable.
30. The processor-based system of claim 22 wherein the memory hub controller is integrated within the system controller.
31. In a memory system having a plurality of memory modules each of which includes a memory hub and a plurality of memory devices, the memory system further having a controller connected to the memory hub in one of the memory modules through a first plurality of bit-lanes, the memory hub in each of the other memory modules being coupled to one of the memory hubs in another of the memory modules, a method of coupling signals between the controller and memory modules, comprising:
if each of the bit-lanes connected between the memory hub in one of the memory modules and the memory hub in another of the memory modules is operable, coupling signals through the respective bit-lanes from the one memory module to the other memory module using the same bit-lanes on which the respective signals were received by the one memory module, and coupling signals through the respective bit-lanes to the one memory module from the other memory module using the same bit-lanes on which the respective signals are transmitted by the one memory module; and
if any of the bit-lanes connected between the memory hub in one of the memory modules and the memory hub in another of the memory modules is inoperable, coupling signals through the respective bit-lanes from the one memory module to the other memory module using bit-lanes that are different from the bit-lanes on which the respective signals were received by the one memory module, and coupling signals through the respective bit-lanes to the one memory module from the other memory module using bit-lanes that are different from the bit-lanes on which the respective signals are transmitted by the one memory module.
32. The method of claim 31 wherein if any of the bit-lanes connected between the memory hub controller and the memory hub in the one memory module is inoperable, coupling signals through the respective bit-lanes from the memory hub controller to the one memory module using bit-lanes that are different from the inoperable bit-lane, and coupling signals through the respective bit-lanes to the memory hub controller from the one memory module using bit-lanes that are different from the inoperable bit-lane.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An illuminated animation device with staggered sources of illumination, the animation device comprising:
a rotatable member rotatable about an axis of rotation;
a first plurality of sources of illumination retained to rotate with the rotatable member;
a second plurality of sources of illumination retained to rotate with the rotatable member;
wherein the first and second pluralities of sources of illumination are actuatable between illuminated and non-illuminated conditions;
wherein the first plurality of sources of illumination are staggered in relation to the second sources of illumination;
whereby, when the rotatable member is rotated and the sources of illumination are actuated, the sources of illumination will produce paths of illumination and whereby the paths of illumination produced by the first plurality of sources of illumination are staggered in relation to the paths of illumination produced by the second plurality of sources of illumination and whereby illuminated images can be displayed by the illuminated animation device with a resolution deriving from the paths of illumination of the first and second pluralities of sources of illumination.
2. The illuminated animation device of claim 1 wherein the rotatable member comprises a rotatable panel with a longitudinal axis of rotation, a first panel half to one side of the longitudinal axis of rotation, and a second panel half to a second side of the longitudinal axis of rotation, wherein the first plurality of sources of illumination are retained in a longitudinally and laterally spaced array by the first panel half, and wherein the second plurality of sources of illumination are retained in a longitudinally and laterally spaced array by the second panel half whereby the illuminated animation device can produce three-dimensional images and animation by a rotation of the rotatable panel in combination with an actuation of the first and second pluralities of sources of illumination.
3. The illuminated animation device of claim 2 wherein the first plurality of sources of illumination are longitudinally staggered in relation to the second plurality of sources of illumination.
4. The illuminated animation device of claim 2 wherein the array of the first plurality of sources of illumination is laterally staggered in relation to the array of the second plurality of sources of illumination.
5. The illuminated animation device of claim 4 wherein the array of the first plurality of sources of illumination is laterally and longitudinally staggered in relation to the array of the second plurality of sources of illumination.
6. The illuminated animation device of claim 1 wherein the first plurality of sources of illumination are retained in a longitudinally and laterally spaced array and wherein the second plurality of sources of illumination are retained in a longitudinally and laterally spaced array spaced from the array of the first plurality of sources of illumination and wherein the first and second pluralities of sources of illumination are rotatable about a longitudinal axis of rotation whereby the illuminated animation device can produce three-dimensional images and animation by a rotation of the rotatable member in combination with an actuation of the first and second pluralities of sources of illumination.
7. The illuminated animation device of claim 6 wherein the array of the first plurality of sources of illumination is disposed substantially in diametric opposition to the array of the second plurality of sources of illumination.
8. The illuminated animation device of claim 6 wherein the first plurality of sources of illumination is approximately equal in number to the second plurality of sources of illumination.
9. The illuminated animation device of claim 6 wherein the array of the first plurality of sources of illumination is disposed in a pattern that substantially matches a pattern in which the array of the second plurality of sources of illumination is disposed.
10. The illuminated animation device of claim 9 wherein the arrays of the first and second pluralities of sources of illumination are substantially evenly spaced, and wherein the arrays of the first and second pluralities of sources of illumination are staggered in lateral and longitudinal positions by approximately one-half a distance between adjacent sources of illumination.
11. The illuminated animation device of claim 1 wherein the first plurality of sources of illumination are retained in a radially spaced array and wherein the second plurality of sources of illumination are retained in a radially spaced array spaced from the array of the first plurality of sources of illumination whereby the illuminated animation device can produce two-dimensional images and animation by a rotation of the rotatable member in combination with an actuation of the first and second pluralities of sources of illumination.
12. The illuminated animation device of claim 11 wherein the array of the first plurality of sources of illumination is disposed substantially in diametric opposition to the array of the second plurality of sources of illumination.
13. The illuminated animation device of claim 11 wherein the pluralities of sources of illumination in each array are substantially evenly spaced and wherein the arrays are staggered in radial position by approximately one-half a distance between adjacent sources of illumination whereby the paths of illumination established by the first plurality of sources of illumination are interposed between the paths of illumination established by the second plurality of sources of illumination.
14. The illuminated animation device of claim 13 wherein the pluralities of sources of illumination are disposed in arrays of substantially straight lines.
15. The illuminated animation device of claim 11 wherein the rotatable member comprises a manually rotatable top with a rotatable body portion and a tip wherein the first and second pluralities of sources of illumination are retained by the body portion of the top.
16. The illuminated animation device of claim 15 wherein animation displayed by the device is calibrated to have a rate of playback as a function of the actual or estimated angular velocity of the top.
17. The illuminated animation device of claim 1 further comprising a circuit board retained to rotate with the rotatable member.
18. The illuminated animation device of claim 1 further comprising a motor for rotating the rotatable member and a power source for powering the motor.
19. The illuminated animation device of claim 1 wherein the rotatable member is rotatable about first and second axes of rotation and wherein the first plurality of sources of illumination are retained in a radially spaced array and wherein the second plurality of sources of illumination are retained in a radially spaced array spaced from the array of the first plurality of sources of illumination whereby the illuminated animation device can produce three-dimensional volumetric images and animation by a rotation of the rotatable member about the first and second axes of rotation in combination with an actuation of the first and second pluralities of sources of illumination.
20. The illuminated animation device of claim 1 wherein the illuminated animation device is handheld with a handle portion that rotatably retains the rotatable member and further comprising a motor for rotating the rotatable member and a power source for powering the motor.
21. The illuminated animation device of claim 20 wherein the rotatable member comprises a rotatable panel with a longitudinal axis of rotation, a first panel half to one side of the longitudinal axis of rotation, and a second panel half to a second side of the longitudinal axis of rotation, wherein the first plurality of sources of illumination are retained in an array by the first panel half, wherein the second plurality of sources of illumination are retained in an array by the second panel half whereby the illuminated animation device can produce three-dimensional images and animation by a rotation of the rotatable panel in combination with an actuation of the first and second pluralities of sources of illumination, wherein the rotatable panel has arrays of apertures entirely therethrough, and wherein the sources of illumination are retained in the apertures in the rotatable panel.
22. The illuminated animation device of claim 21 further comprising a user control interface for permitting selective control of the rotation of the rotatable member, the illumination of the sources of illumination, and the animation speed of three-dimensional animation displayed by the animation device.
23. The illuminated animation device of claim 22 further comprising a power circuit board retained by the handle portion, a display circuit board retained to rotate with the rotatable member, rotary electrical interfaces for transmitting power and control signals between the power circuit board and the display circuit board, a memory chip retained to rotate with the rotatable member, a data connector in electrical communication with the memory chip for loading data files onto the memory chip, and a programming connector retained to rotate with the rotatable member to permit a programming of the display circuit board.
24. The illuminated animation device of claim 22 further comprising means for adjusting the brightness of the sources of illumination dependent on a distance of the source of illumination from the axis of rotation.