1. A method implemented in one or more data processing systems, comprising:
receiving a geometric model including at least one removal feature having at least one face;
designating at least one face as a remove variational face;
adding a constraint that refers to the designated face;
creating a second object corresponding to the removal feature;
modifying the constraint to refer to the second object instead of the removal feature;
removing the removal feature;
performing a variational edit and solve on the model using the second object in place of the removal feature; and
recreating the model according to the variational edit, the recreated model including the removal feature placed according to an updated location of the second object.
2. The method of claim 1, wherein performing the variational edit includes moving a location of the second object in the model according to the constraint.
3. The method of claim 1, wherein the removal feature must be removed from the model before the model can be solved.
4. A data processing system comprising:
a processor; and
an accessible memory,
the data processing system particularly configured to
designate at least one face as a remove variational face;
add a constraint that refers to the designated face;
create a second object corresponding to the removal feature;
modify the constraint to refer to the second object instead of the removal feature;
remove the removal feature;
perform a variational edit and solve on the model using the second object in place of the removal feature; and
recreate the model according to the variational edit, the recreated model including the removal feature placed according to an updated location of the second object.
5. A non-transitory computer-readable medium encoded with computer-executable instructions that, when executed, cause a data processing system to perform the steps of:
designating at least one face as a remove variational face;
adding a constraint that refers to the designated face;
creating a second object corresponding to the removal feature;
modifying the constraint to refer to the second object instead of the removal feature;
removing the removal feature;
performing a variational edit and solve on the model using the second object in place of the removal feature; and
recreating the model according to the variational edit, the recreated model including the removal feature placed according to an updated location of the second object.
6. A method implemented in one or more data processing systems, comprising:
receiving a geometric model including at least one removal feature having at least one face;
creating a second object that is associated with the removal feature;
adding a constraint to the second object;
removing the removal feature from the model and adding a temporary topology to the model to support the removing, the temporary topology being substantially identical to the second object;
binding the temporary topology and the second object;
performing a variational edit and solve on the model using the second object to position the temporary topology in the model; and
recreating the model according to the variational edit, the recreated model including the removal feature placed according to the location of the temporary topology.
7. The method of claim 6, wherein the binding requires that the temporary topology and the second object are moved and changed in the same way during an edit.
8. The method of claim 6, wherein the temporary topology and the second object are discarded after the model is recreated.
9. A data processing system comprising:
a processor; and
an accessible memory,
the data processing system particularly configured to
receive a geometric model including at least one removal feature having at least one face;
create a second object that that is associated with the removal feature;
add a constraint to the second object;
remove the removal feature from the model and adding a temporary topology to the model to support the removing, the temporary topology being substantially identical to the second object;
bind the temporary topology and the second object;
perform a variational edit and solve on the model using the second object to position the temporary topology in the model; and
recreate the model according to the variational edit, the recreated model including the removal feature placed according to the location of the temporary topology.
10. A non-transitory computer-readable medium encoded with computer-executable instructions that, when executed, cause a data processing system to perform the steps of:
receiving a geometric model including at least one removal feature having at least one face;
creating a second object that is associated with the removal feature;
adding a constraint to the second object;
removing the removal feature from the model and adding a temporary topology to the model to support the removing, the temporary topology being substantially identical to the second object;
binding the temporary topology and the second object;
performing a variational edit and solve on the model using the second object to position the temporary topology in the model; and
recreating the model according to the variational edit, the recreated model including the removal feature placed according to the location of the temporary topology.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power source, comprising:
a primary power source control circuit configured to couple a primary power source to an output;
a backup power source control circuit configured to couple a backup power source to the output;
wherein at least one of the primary power source control circuit and the backup power source control circuit comprises a first transistor and a second transistor coupled in series between the output and the primary power source or the backup power source, respectively; and
a resistive element coupled between a node between the first transistor and the second transistor and a ground node.
2. The power source of claim 1, wherein each of the primary power source control, circuit and the backup power source control circuit respectively comprise the first transistor and the second transistor coupled in series.
3. The power source of claim 2, wherein a gate of the first transistor of the backup power source control circuit and a gate of the second transistor of the backup power source control circuit are each coupled to the primary power source.
4. The power source of claim 2, the first transistor of the backup power source control circuit and the second transistor of the backup power source control circuit serially couple the backup power source to the output when the primary power source is disabled.
5. The power source of claim 1, wherein the primary power source is provided to the output when enabled.
6. The power source of claim 1, wherein a voltage level of the primary power source is greater than a voltage level of the backup power source.
7. A power source control circuit, comprising:
a first transistor coupled to a primary power source, wherein a gate of the first transistor is coupled to an input;
a second transistor coupled in series with the first transistor and to an output, wherein the first transistor and the second transistor are configured to couple the primary power source to the output responsive to the primary power source being enabled, and wherein the first transistor and the second transistor are configured to decouple the primary power source from the output responsive to the primary power source being disabled; and
a backup power source control circuit coupled to the output and to the primary power source.
8. The power source control circuit of claim 7, wherein a gate of the second transistor is coupled to the input.
9. The power source control circuit of claim 7, wherein the first transistor and the second transistor include respective inherent diodes.
10. The power source control circuit of claim 9, wherein a polarity of the inherent diode of the first transistor is coupled to have the same as a polarity of the inherent diode of the second transistor.
11. The power source control circuit of claim 7, wherein the backup power source control circuit is configured to provide a backup power source to the output when the primary power source is disabled.
12. The power source control circuit of claim 7, wherein the backup power source control circuit comprises a third transistor coupled in series with a fourth transistor, wherein the fourth transistor is coupled to the output.
13. The power source control circuit of claim 12, wherein a gate of the third transistor and a gate of the fourth transistor are coupled to the primary power source.
14. The power source control circuit of claim 12, wherein the third transistor is coupled to a backup power source.
15. A method, comprising:
receiving a power source at a primary power control circuit;
enabling a first transistor the power control circuit and a second transistor of the primary power control circuit responsive to the power source being enabled, wherein the first transistor is coupled in series with the second transistor;
disabling a backup power source control circuit responsive to the power source being enabled;
providing the power source to an output through the enabled first transistor and the enabled second transistor; and
discharging a node between the first transistor and the second transistor to a reference via a resistive element responsive to the power source being disabled.
16. The method of claim 15, further comprising disabling the first transistor and the second transistor responsive to the power source being disabled.
17. The method of claim 15, further comprising enabling a backup power source control circuit responsive to the power source being disabled.
18. The method of claim 17, further comprising providing a backup power source to the output responsive to the backup power source control circuit being enabled.
19. The method of claim 17, wherein enabling a backup power source control circuit comprises enabling a third transistor and a fourth transistor.
20. The method of claim 17, wherein the third transistor is coupled in series with the fourth transistor.
21. The method of claim 15, further comprising receiving a backup power source at the backup power source control circuit.
22. A power source control circuit, comprising:
a first transistor coupled to a primary power source;
a second transistor coupled in series with the first transistor and to an output, wherein the first transistor and the second transistor are configured to couple the primary power source to the output responsive to the primary power source being enabled, and wherein the first transistor and the second transistor are configured to decouple the primary power source from the output responsive to the primary power source being disabled;
a resistive element coupled between a node between the first transistor and the second transistor and a ground node; and
a backup power source control circuit coupled to the output and to the primary power source.