1. A flash memory system, comprising:
a flash memory configured to perform a read operation using a plurality of read levels; and
a memory controller configured to recover original data using a counter value provided from the flash memory,
wherein the flash memory converts read result values obtained using the plurality of read levels into the counter value to provide the counter value to the memory controller.
2. The flash memory system of claim 1, wherein the flash memory includes:
read counter logic configured to convert the read result values obtained using the plurality of read levels into the counter value.
3. The flash memory system of claim 2, wherein the read counter logic includes a log2 n bit counter, wherein n is the number of the plurality of read levels.
4. The flash memory system of claim 2, wherein the counter value is 0 or 1.
5. The flash memory system of claim 1, wherein the flash memory stores m-bit data in a memory cell, wherein m is an integer of 1 or more.
6. The flash memory system of claim 1, wherein the memory controller includes:
a code modulation encoder configured to convert the original data into code modulation data.
7. The flash memory system of claim 6, wherein the code modulation encoder comprises:
a bit divider which divides the original data into a plurality of messages;
an error correction code (ECC) encoder which performs ECC encoding on each of the messages to output a code word associated with each of the messages; and
a subset and state selector which performs a bit-state mapping operation on the code words to output the code modulation data.
8. The flash memory system of claim 7, wherein the bit divider determines a size of each of the messages based on an error correction capacity of the ECC encoder.
9. The flash memory system of claim 8, wherein the ECC encoder generates parities such that the code words associated with the messages have the same size.
10. The flash memory system of claim 1, wherein the flash memory and the memory controller are included in a memory card.
11. The flash memory system of claim 1, wherein the flash memory and the memory controller are included in a solid state drive.
12. The flash memory system of claim 1, wherein the flash memory has a three-dimensional structure.
13. A flash memory, comprising:
a memory cell array configured to store data; and
a control unit configured to perform a read operation using a plurality of read levels to read data stored in the memory cell array,
wherein the control unit converts read result values obtained using the plurality of read levels into a counter value.
14. The flash memory of claim 13, wherein the control unit includes:
read counter logic configured to convert the read result values obtained using the plurality of read levels into the counter value.
15. The flash memory system of claim 14, wherein the read counter logic includes a log2 n bit counter, wherein n is the number of the plurality of read levels.
16. The flash memory system of claim 13, wherein the counter value is provided to a memory controller.
17. The flash memory system of claim 13, wherein the counter value is preset data.
18. A memory system, comprising:
a nonvolatile memory configured to perform a plurality of read operations on a memory cell using a plurality of read levels and output data having a number of bits less than the number of read levels; and
a memory controller configured to receive the data output from the nonvolatile memory.
19. The memory system of claim 18, wherein log2 n*N bits are transferred for a word line when the number of memory cells connected with the word line is N, wherein n is the number of the plurality of read levels.
20. The memory system of claim 18, wherein the memory controller provides the nonvolatile memory with code modulation data including bit-state mapping information.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multiprocessor wireless communication device comprising:
a security processor to combine a plurality of key-shares, including at least a first key-share, a second key-share, and a device-dependent key-share, to generate a decryption key to decrypt content for the processing system, the security processor to monitor usage of the content and to purge at least one of the key-shares when the usage exceeds a measurment parameter;
a communications processor to play decrypted content recieved from the security processor; and
a radio-frequency (RF) interface to receive the first and second of the key-shares and encrypted content over a wireless communication link in response to a request to access the content and verification of a user’s credit,
wherein the wireless communication device has the device-dependant key-share pre-stored in a processor area,
wherein the security processor authenticates the measurment parameters with an authentication code to help prevent tampering with the measurment parameters, and
wherein the measurement parameters are secured by the authentication code and provided by a security server over the wirelss link along with the encrytped content or when the authentication code fails to authenticate.
2. The wireless communication device of claim 1 wherein the security processor portion purges at least one of the key-shares when usage of the content exceeds a service limit indicated by the measurment parameters.
3. The wireless communication device of claim 2, wherein the security processor retrieves a user-dependant key-share from a subscriber identity module (SIM) inserted into the wirelss communication device, and receives the second key-share from a finance server when the user’s credit is verified for accessing the content.
4. The wireless communication device of claim 3 wherein the measurment parameters comprise at least one of a date-limit, a run-time limit, and an iteration limit.
5. The wireless communication device of claim 4 further comprising an applications processor located within the processor area to process applications running on the wireless communication device, and
wherein the security processor, the communications processor and the applications processor are fabricated within an application specific integrated circuit (ASIC).
6. The wireless communication device of claim 5 further comprising a module recieving area to recieve the subscriber identity module (SIM), the SIM having the user-dependant key-share pre-stored therin.
7. The wireless communication device of claim 1 wherein the storage of the decrypted content is prohibited.