1. A semiconductor device, comprising:
a substrate;
a gate electrode located over the substrate, the gate electrode having an upper surface; and
a dielectric material disposed within the gate electrode, the dielectric material extending from the upper surface toward the substrate.
2. The device of claim 1, wherein the dielectric material extends completely through the gate electrode.
3. The device of claim 1, wherein the substrate includes an active region and a dielectric region that forms an interface with the active region, the dielectric material being located near a region of the gate electrode that is above the interface.
4. The device of claim 1, wherein the dielectric material includes a first edge having a first dimension and a second edge having a second dimension that is greater than the first dimension.
5. The device of claim 4, wherein the second dimension is greater than about 0.2 um.
6. The device of claim 4, further including spacers formed on either side of the gate electrode, the spacers having a third dimension, wherein the first dimension is less than about two times the third dimension.
7. The device of claim 4, wherein a first voltage is a gate voltage that induces a first channel in a first region of the semiconductor device that is away from the interface, and a second voltage is the gate voltage that induces a second channel in a second region of the semiconductor device that is near the interface, and wherein the first and second dimensions are functions of the first and second voltages.
8. The device of claim 7, wherein the first and second dimensions are implemented in a manner so that the first voltage is approximately equal to the second voltage.
9. A semiconductor device, comprising:
a gate having first, second, third, and fourth edges that together define the gate, the first and second edges being disposed on opposite sides, the third and fourth edges being disposed on opposite sides;
first and second spacers formed adjacent to the first and second edges of the gate, respectively; and
a dielectric structure disposed within the gate, the dielectric structure being located near the third edge.
10. The device of claim 9, wherein the gate includes a further dielectric structure that is located near the fourth edge.
11. The device of claim 9, wherein the first and second edges extend in a first direction, and the third and fourth edges extend in a second direction, and wherein the dielectric structure includes:
a first dimension measured in the first direction; and
a second dimension measured in the second direction;
wherein the first dimension is greater than the second dimension.
12. The device of claim 11, wherein the first dimension is greater than about 0.2 um.
13. The device of claim 11, wherein one of the first and second spacers has a third dimension measured in the second direction, and wherein the second dimension is smaller than about two times the third dimension.
14. The device of claim 9, wherein the dielectric structure includes a material that is substantially the same as a material of the first and second spacers.
15. The device of claim 9, wherein the gate is located above a substrate, the substrate including a doped region and a insulating region that forms an interface with the doped region, and wherein the dielectric structure is located above the interface.
16. The device of claim 15, wherein the doped region includes source and drain regions and a guard ring region, the source and drain regions being encircled by the insulating region, the insulating region being encircled by the guard ring region.
17. A semiconductor device, comprising:
a layer having an active region and a dielectric region that forms an interface with the active region;
a gate electrode located above a portion of the active region and a portion of the dielectric region; and
a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region.
18. The device of claim 17, wherein the dielectric material extends completely through the gate electrode.
19. The device of claim 17, further including a gate dielectric that is disposed between the layer and the gate electrode.
20. The device of claim 17, further including gate spacers formed on either side of the gate electrode, the gate spacers having a material that is substantially the same as the dielectric material that is disposed within the gate electrode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cationic lipid selected from the group consisting of: Bn-DHxRIE, DHxRIE-OAc, DHxRIE-OBz and Pr-DOctRIE-OAc.
2. The cationic lipid of claim 1, wherein said lipid is Bn-DHxRIE.
3. The cationic lipid of claim 1, wherein said lipid is DHxRIE-OAc.
4. The cationic lipid of claim 1, wherein said lipid is DHxRIE-OBz.
5. The cationic lipid of claim 1, wherein said lipid is Pr-DOctRIE-OAc.
6. A method of producing a sterile formulation comprising:
(a) mixing
(i) a cationic surfactant selected from the group consisting of Bn-DHxRIE, DHxRIE-OAc, DHxRIE-OBz and Pr-DOctRIE-OAc;
(ii) a polyoxyethylene (POE) and polyoxypropylene (POP) block copolymer; and
(iii) a polynucleotide;
at a temperature below the cloud point of said block copolymer to form a mixture; and
(b) cold filtering the mixture to produce a sterile formulation.
7. The method of claim 6, further comprising aliquoting said formulation into a suitable container.
8. The method of claim 6, wherein said block copolymer is of the general formula:
HO(C2H4O)x(C3H6O)y(C2H4O)xH; wherein (y) represents a number such that the molecular weight of the hydrophobic POP portion (C3H6O) is up to approximately 20,000 daltons and wherein (x) represents a number such that the percentage of the hydrophilic POE portion (C2H4O) is between approximately 1% and 50% by weight.
9. The method of claim 8, wherein said block copolymer is the poloxamer CRL-1005.
10. The method of claim 6, wherein said block copolymer is of the general formula: HO(C3H6O)y(C2H4O)x(C3H6O)yH wherein (y) represents a number such that the molecular weight of the hydrophobic POP portion (C3H6O) is up to approximately 20,000 daltons and wherein (x) represents a number such that the percentage of hydrophilic POE portion (C2H4O) is between approximately 1% and 50% by weight.
11. The method of claim 6, wherein said mixing is performed at a temperature of about \u22122\xb0 C. to about 8\xb0 C.
12. The method of claim 6, wherein said cold filtering is performed at a temperature of about \u22122\xb0 C. to about 8\xb0 C.
13. The method of claim 6, wherein said cold filtering is performed using a filter with a pore size of about 0.01 microns to about 2 microns.
14. The method of claim 6, wherein the final concentration of said cationic surfactant present in said formulation is from about 0.01 mM to about 5 mM.
15. The method of claim 6, wherein the final concentration of said block copolymer present in said formulation is from about 1 mgmL to about 50 mgmL.
16. The method of claim 6, wherein the final concentration of said polynucleotide present in said formulation is from about 1 ngmL to about 10 mgmL.
17. The method of claim 6, wherein said cationic surfactant is Bn-DHxRIE.
18. The method of claim 6, wherein said cationic surfactant is DHxRIE-OAc.
19. The method of claim 6, wherein said cationic surfactant is DHxRIE-OBz.
20. The method of claim 6, wherein said cationic surfactant is Pr-DOctRIE-OAc.
21. The method of claim 6, wherein said method does not include raising the temperature of the mixture above the cloud point of said block copolymer.