What is claimed is:
1. An exercise apparatus, comprising:
a frame having a base that is configured to rest upon a floor surface;
a left crank and a right crank, wherein each said crank is rotatably mounted on the frame;
a left rocker link and a right rocker link, wherein each said rocker link is pivotally mounted on the frame;
a left bar and a right bar, wherein each said bar has a first end rotatably connected to a respective crank;
first and second left intermediate links, wherein each of said left intermediate links is pivotally interconnected between the left rocker link and an opposite, second end of the left bar;
first and second right intermediate links, wherein each of said right intermediate links is pivotally interconnected between the right rocker link and an opposite, second end of the right bar; and
a left foot support and a right foot support, wherein each said foot support is supported by an intermediate portion of a respective bar and constrained to move through a generally elliptical path in response to rotation of each said crank.
2. The exercise apparatus of claim 1, wherein an upper distal end of one of the left intermediate links is sized and configured for grasping, and an upper distal end of one of the right intermediate links is sized and configured for grasping.
3. The exercise apparatus of claim 2, wherein said one of the left intermediate links is pivotally connected to a distal end of the left rocker link, and said one of the right intermediate links is pivotally connected to a distal end of the right rocker link.
4. The exercise apparatus of claim 1, wherein each said rocker link pivots through a range of generally horizontal orientations.
5. The exercise apparatus of claim 4, wherein said intermediate links pivot through a range of generally vertical orientations.
6. The exercise apparatus of claim 1, wherein each said foot support is movably mounted on a respective bar and operatively connected to a respective one of the intermediate links.
7. The exercise apparatus of claim 6, wherein a left connector link has a first end pivotally connected to the respective one of the left intermediate links, and a second end pivotally connected to the left foot support, and a right connector link has a first end pivotally connected to the respective one of the right intermediate links, and a second end pivotally connected to the right foot support.
8. The exercise apparatus of claim 7, wherein the first end of each said connector link is selectively movable along a respective one of the intermediate links to adjust the elliptical path of each said foot support.
9. The exercise apparatus of claim 8, wherein the first end of each said connector link is pivotally connected to a bracket, and each said bracket is slidably mounted on a respective one of the intermediate links.
10. The exercise apparatus of claim 9, wherein each said bracket is threadably mounted on a respective lead screw, and each said lead screw is operatively connected to a respective motor, and each said motor is mounted on a respective one of the intermediate links.
11. An exercise apparatus, comprising:
a frame having a base that is configured to rest upon a floor surface;
a left crank and a right crank, wherein each said crank is rotatably mounted on the frame;
a left bar and a right bar, wherein each said bar has a first end rotatably connected to a respective crank;
a left foot support and a right foot support, wherein each said foot support is supported by an intermediate portion of a respective bar;
a left guiding means for guiding an opposite, second end of the left bar through a closed loop in response to rotation of said left crank; and
a right guiding means for guiding an opposite, second end of the right bar through a closed loop in response to rotation of said right crank, wherein each said guiding means includes a rocker link pivotally mounted on the frame, and at least one intermediate link pivotally interconnected between a respective rocker link and a respective bar.
12. The exercise apparatus of claim 11, wherein on each side of the frame, an upper distal end of one said intermediate link moves through a generally elliptical path and is sized and configured for grasping.
13. The exercise apparatus of claim 11, wherein each said foot support is movably mounted on a respective bar, and on each side of the frame, a drawbar link is pivotally interconnected between one said intermediate link and a respective foot support.
14. The exercise apparatus of claim 13, further comprising a means for adjusting where each said drawbar link is pivotally connected to a respective intermediate link.
15. The exercise apparatus of claim 11, wherein each said guiding means includes first and second intermediate links pivotally interconnected between a respective rocker link and a respective bar.
16. An exercise apparatus, comprising:
a frame having a base that is configured to rest upon a floor surface;
a left crank and a right crank, wherein each said crank is rotatably mounted on the frame;
a left bar and a right bar, wherein each said bar has a first end rotatably connected to a respective crank;
a left foot support and a right foot support, wherein each said foot support is supported by an intermediate portion of a respective bar; and
a left rocker assembly and a right rocker assembly, wherein each said rocker assembly includes three links, and at least one of the links is pivotally connected to the frame, and at least one of the links is pivotally connected to a respective bar, and each of the links is pivotally connected to at least one other of the links, thereby constraining each said foot support to move through a generally elliptical path.
17. The exercise apparatus of claim 16, wherein a first one of the links is pivotally connected to the frame, and a second one of the links is pivotally interconnected between the bar and the first one of the links, and a third one of the links is pivotally interconnected between the bar and the first one of the links.
18. The exercise apparatus of claim 16, wherein a respective handle is provided on an upper end of one of the links in each said rocker assembly.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A high speed digital circuit for use with an N bit digital data signal comprising:
a. a source device for receiving said N bit digital data signal;
b. a sink device coupled to said source device and receiving said N bit digital data signal from said source device, said N bit digital data signal having a skew when received by said sink device;
c. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal;
d. a compensation circuit in said source device for receiving said skew detection signal and compensating for said skew in said N bit digital data signal in response thereto.
2. The circuit of claim 1, wherein said source device outputs a reference signal to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal.
3. The circuit of claim 2, wherein said skew detection circuit includes a circuit for detecting the skew of each of said N bits in said N bit digital data signal, generating N phase detection signals in response thereto, and multiplexing said N phase detection signals as said skew detection signal.
4. The circuit of claim 2, wherein said source device is a high complexity integrated circuit, and said sink device is a low complexity integrated circuit.
5. The circuit of claim 2, and further comprising a line for supplying a synchronization signal between said source device and said sink device.
6. The circuit of claim 5, wherein said source device includes N variable delay units for outputting said N bits, each of said variable delay units associated with and individually controlled by a respective one bit of a phase comparison signal.
7. The circuit of claim 6, wherein said source device includes a counter circuit for supplying said reference signal to said sink device.
8. The circuit of claim 7, wherein said source device includes a delay control circuit for supplying said phase comparison signal as a control signal to said N variable delay units.
9. The circuit of claim 8, wherein said source device includes N low pass filters, each of said low pass filters coupled to one of said N variable delay units, said N low pass filters being disposed between said delay control circuit and said N variable delay units.
10. The circuit of claim 9, wherein said sink device includes N phase detectors for outputting a phase comparison in response to a respective one of said N bits and said reference signal.
11. The circuit of claim 10, wherein said sink device includes a counter circuit for receiving said reference signal from said source device.
12. The circuit of claim 11, wherein said sink device includes a skew signal circuit coupled to said counter circuit and said N phase detectors for supplying said skew detection signal to said source device.
13. The circuit of claim 12, wherein said sink device includes N analog to digital converters coupled to said N phase detectors and said skew signal circuit.
14. The circuit of claim 13, and further comprising a line for supplying said synchronization signal between said counter circuits in said source device and said sink device.
15. The circuit of claim 14, wherein said sink device includes N low pass filters, each of said low pass filters connected between one of said N phase detectors and one of said N analog to digital converters.
16. The circuit of claim 1, wherein said high speed digital circuit operates in an initialization condition in which a digital initialization signal having bits of a first predefined unit length initializes said circuit, and in an operating condition in which said N bits of said N bit digital data signal have a second predefined unit length, wherein said source device includes N AND gates for receiving said N bit digital data signal and said digital initialization signal to produce a gated N bit digital data signal, and variable delay units for receiving said gated N bit digital data signal and outputting an N bit data signal in response thereto, and wherein said first predefined unit length is greater than said second predefined unit length.
17. The circuit of claim 1, and further comprising a line for supplying a reference signal from said source device to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal, and wherein said sink device includes N correlator units for detecting the delay between each of the N bits of said N bit digital data signal and said reference signal and outputting a phase detection signal.
18. The circuit of claim 1, wherein said sink device inserts a synchronization signal in said skew detection signal supplied to said source device, and wherein said source device includes a sync circuit for receiving said synchronization signal and synchronizing said source device with said sink device in response thereto.
19. A method of correcting the skew in an N bit digital data signal transmitted between a source device and a sink device of an interface, comprising the steps of:
a. measuring said skew in said N bit digital data signal in said sink device;
b. generating a skew detection signal in said sink device;
c. transmitting said skew detection signal from said sink device to said source device; and
d. compensating for said skew in said N bit digital data signal in said source device in response to said skew detection signal.
20. The method of claim 19, and further comprising the step of supplying a reference signal from said source device to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal.
21. The method of claim 20, and further comprising the steps of:
a. detecting the skew of each of the N bits in said N bit digital data signal;
b. generating N phase detection signals in response thereto; and
c. multiplexing said N phase detection signals as said skew detection signal.
22. The method of claim 20, and further comprising the step of supplying a synchronization signal between said source device and said sink device.
23. The method of claim 22, wherein said interface operates in an initialization condition and in an operating condition, and further comprising the steps of:
a. transmitting, in said operating condition, said N bit digital data signal with bits having a first predefined unit length; and
b. transmitting, in said initialization condition, a digital data signal with bits having a second predefined unit length, said second predefined unit length greater than said first predefined unit length.
24. A high speed digital interface circuit for use with an N bit digital data signal comprising:
a. an N bit bus connecting a source device and a sink device, said N bit digital data signal being received at said sink device with a skew;
b. said source device comprising:
i. N variable delay units, each associated with one of said N bits, and each of said variable delay units individually controlled for each of said N bits;
ii. a compensation circuit in said source device for compensating for said skew, said compensation circuit including:
1. a counter circuit for supplying a reference signal to said sink device;
2. an AND gate coupled to said counter circuit; and
3. N low pass filters, each associated with one of said N bits, and each of said low pass filters coupled to one of said N variable delay units and to said AND gate;
c. said sink device comprising:
i. N phase detectors, each associated with one of said N bits, and each of said phase detectors individually controlled for each of said N bits by said reference signal;
ii. N analog to digital converters, each associated with one of said N bits, coupled to said N phase detectors;
iii. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal, said skew detection circuit including:
1. a counter circuit for receiving said reference signal from said source device; and
2. an AND gate coupled to said counter circuit;
d. a line supplying said skew detection signal from said sink device to said source device; and
e. a line supplying said reference signal from said source device to said sink device.
25. The circuit of claim 24, and further comprising a line for supplying a synchronization signal between said counter circuits in said source device and said sink device.
26. The circuit of claim 24, wherein said skew detection circuit detects the skew of each of said N bits in said N bit digital data signal, generates N phase detection signals, each associated with one of said N bits in response thereto, and multiplexes said N phase detection signals as said skew detection signal.
27. The circuit of claim 24, wherein said source device is a high complexity integrated circuit, and said sink device is a low complexity integrated circuit.
28. The circuit of claim 24, wherein said high speed digital interface circuit operates in an initialization condition in which a digital initialization signal having bits of a first predefined unit length initializes said circuit, and in an operating condition in which said N bits of said N bit digital data signal have a second predefined unit length, wherein said source device includes N AND gates, each associated with one of said N bits, for receiving said N bit digital data signal and said digital initialization signal, and wherein said first predefined unit length is greater than said second predefined unit length.
29. The circuit of claim 24, wherein said phase detectors in said sink device are correlator units for detecting the delay between each of the N bits of said N bit digital data signal and said reference signal.
30. The circuit of claim 24, wherein said sink device inserts a synchronization signal in said skew detection signal supplied to said source device, and wherein said source device includes a sync circuit for receiving said synchronization signal and synchronizing said counters in said source device and said sink device.