1. A semiconductor device, comprising:
a clock input unit configured to receive a system clock and a data clock externally;
a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference;
a phase detecting unit configured to detect phase differences between one of the plurality of multi-system clocks and the data clock to generate a training information signal in response to the detection result; and
a signal transmitting unit configured to transmit the training information signal,
wherein the phase detecting unit includes:
a plurality of phase comparing units configured to compare phases between each of the plurality of multi-system clocks and the data clock, respectively, to output a plurality of comparison signals; and
a logic level changing unit configured change a logic level of the training information signal in response to the plurality of comparison signals,
wherein the data clock and the plurality of multi-system clocks have the same frequency.
2. The semiconductor device of claim 1, wherein the phase dividing unit is configured to generate the plurality of multi-system clocks with a phase difference of 45\xb0 from each other, a phase difference of 90\xb0 from each other, or a phase difference of 180\xb0 from each other in response to the system clock.
3. The semiconductor device of claim 1, wherein each of the phase comparing units is configured to determine whether the comparison signals are activated or not according to an activation state of the data clock at times when a logic level of any one clock among the plurality of multi-system clocks is being changed.
4. The semiconductor device of claim 1, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when all the plurality of comparison signals outputted from the plurality of phase comparing units are activated.
5. The semiconductor device of claim 1, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when all the plurality of comparison signals outputted from the plurality phase comparison units are inactivated.
6. The semiconductor device of claim 1, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when the number of the comparison signals of inactivated states is greater than the number of the comparison signals of activated states among the comparison signals outputted from the plurality of the phase comparing units.
7. The semiconductor device of claim 1, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when the number of the comparison signals of activated states is greater than the number of the comparison signals of inactivated states among the comparison signals outputted from the plurality of the phase comparing units.
8. A semiconductor device, comprising:
a clock input unit configured to receive a system clock and a data clock externally;
a phase dividing unit configured to generate a plurality of multi-system clocks each having an individual phase difference based on the system clock;
a clock dividing unit configured to generate a data dividing clock with the same frequency as the plurality of multi-system clocks by dividing a frequency of the data clock;
a phase detecting unit configured to detect phase differences between the plurality of multi-system clocks and the data dividing clock to generate a training information signal in response to the detection result; and
a signal transmitting unit configured to transmit the training information signal,
wherein the phase detecting unit includes:
a plurality of phase comparing units configured to compare phases between each of the plurality of multi-system clocks and the data dividing clock, respectively, to output a plurality of comparison signals; and
a logic level changing unit configured to change a logic level of the training information signal in response to the plurality of comparison signals.
9. The semiconductor device of claim 8, wherein the phase dividing unit is configured to generate the plurality of multi-system clocks with a phase difference of 45\xb0 from each other, a phase difference 90\xb0 from each other, or a phase difference 180\xb0 from each other in response to the system clock.
10. The semiconductor device of claim 8, wherein each of the phase comparing units determines whether the comparison signals are activated or not according to an activation state of the data dividing clock at times when a logic level of any one clock among the plurality of multi-system clocks is being changed.
11. The semiconductor device of claim 8, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when all the plurality of comparison signals outputted from the plurality of phase comparing units are activated.
12. The semiconductor device of claim 8, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when all the plurality of comparison signals outputted from the plurality phase comparison units are inactivated.
13. The semiconductor device of claim 8, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when the number of the comparison signals of inactivated states is greater than the number of the comparison signals of activated states among the comparison signals outputted from the plurality of the phase comparing units.
14. The semiconductor device of claim 8, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when the number of the comparison signals of activated states is greater than the number of the comparison signals of inactivated states among the comparison signals outputted from the plurality of the phase comparing units.
15. A semiconductor device, comprising:
a clock input unit configured to receive a system clock and a data clock from outside;
a first clock dividing unit configured to divide a frequency of the system clock by a first ratio to output a system dividing clock;
a phase dividing unit configured to generate a plurality of multi-system dividing clocks having a phase difference of a dedicated size respectively in response to the system dividing clock;
a second clock dividing unit configured to divide a frequency of the data clock by a second ratio to generate a data dividing clock;
a phase detecting unit configured to detect phase differences between the plurality of multi-system dividing clocks and the data dividing clock respectively to generate a training information signal in response to the detection result; and
a signal transmitting unit configured to transmit the training information signal,
wherein the phase detecting unit includes:
a plurality of phase comparing units configured to compare phases between the plurality of multi-system dividing clocks and the data dividing clock, respectively, to output a plurality of comparison signals; and
a logic level changing unit configured to change a logic level of the training information signal in response to the comparison signals output from the phase comparing units,
wherein the data dividing clock and the plurality of multi-system dividing clocks have the same frequency.
16. The semiconductor device of claim 15, wherein the phase dividing unit is configured to generate the plurality of multi-system dividing clocks with a phase difference of 45\xb0 from each other, a phase difference 90\xb0 from each other or a phase difference 180\xb0 from each other in response to the system dividing clock.
17. The semiconductor device of claim 15, wherein each of the phase comparing units is configured to determine whether the comparison signals are activated or not according to activation state of the data dividing clock at a time when a logic level of any one clock among the plurality of multi-system dividing clocks is changed.
18. The semiconductor device of claim 15, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when all the plurality of comparison signals outputted from the plurality of phase comparing units are activated.
19. The semiconductor device of claim 15, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when all the plurality of comparison signals outputted from the plurality phase comparison units are inactivated.
20. The semiconductor device of claim 15, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when the number of the comparison signals of inactivated states is greater than the number of the comparison signals of activated states among the comparison signals outputted from the plurality of the phase comparing units.
21. The semiconductor device of claim 15, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when the number of the comparison signals of activated states is greater than the number of the comparison signals of inactivated states among the comparison signals outputted from the plurality of the phase comparing units.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A transistor device laid out in a CMOS process, shaped as a rectangle having four edges, comprising:
a first drainsource layer that is employable as a source or a drain connection layer;
a top drainsource layer that is employable as a source or a drain connection layer, wherein said top drainsource layer is above said first drainsource layer, and wherein both of said first drainsource layer and said top drainsource layer covers each of said four edges of said device rectangle, such that both of said drain and said source are accessible from each of said four edges of said device rectangle;
two or more via stripes extending over an entire length in an X direction and evenly distributed over an entire length in a Y direction connecting said first drainsource layer and said top drainsource layer;
a gate layer that is employable as a gate connection layer; and
a bulk layer that is employable as a bulk connection layer, wherein the bulk is independently accessible from the drain, the gate, and the source.
2. The transistor device of claim 1, wherein said first drainsource layer and said top drainsource layer are both metal layers.
3. The transistor device of claim 1, wherein said gate layer is connected to a plurality of polysilicon gates in said X direction underlying said gate layer wherein said polysilicon gates are transistor fingers wherein said transistor fingers extend over an entire length of said rectangle in said Y direction.
4. The transistor device of claim 3 wherein said via stripes are evenly distributed over a length of said transistor fingers in said Y direction.
5. The transistor device of claim 1, wherein said first drainsource layer, said top drainsource layer, said gate layer, and said bulk layer are all metal layers.
6. The transistor device of claim 5, wherein
said bulk layer is a Metal 1 layer that is below said gate layer, said first drainsource layer, and said top drainsource layer;
said gate layer is a Metal 2 layer that is below said first drainsource layer and said top drainsource layer; and
wherein said first drainsource layer is a Metal 3 layer that is below said top drainsource layer.
7. The transistor device of claim 1, wherein
said transistor device is a transistor array including a plurality of transistors;
said first drainsource layer is connected to said drain or said source of each transistor of a plurality of transistors;
said top drainsource layer is connected to said drain or said source of each of said plurality of transistors;
each transistor in said plurality of transistors is shaped as a rectangle having four edges;
each of said transistors in said plurality is structured such that any two transistors having any two edges abutting each other automatically have their gates, drains, sources, edges, and bulks coupled together; and
wherein, for each of said transistors in said plurality, at least one edge of said transistor is abutted to at least one of said edges of at least one of another of said transistors in said plurality of transistors.