1. A sheet fed offset printing machine for printing and processing sheets comprising:
a plurality of sheet fed offset printing units each including an arrangement of a plate cylinder adapted for carrying a printing plate, a blanket or press cylinder in adjacent contacting relation to the plate cylinder, and an impression cylinder free of contact with the plate cylinder in adjacent contacting relation to the blanket or press cylinder for defining a sheet passage nip therebetween,
one of said printing units being a coating printing unit having a supply of adhesive material and the plate cylinder and blanket cylinder of said coating printing unit being operable for applying an image forming adhesive coating onto sheets passing through the sheet passage nip of the one printing unit, and
one of said printing units having an integrated transfer foil apparatus comprising a structural unit that includes a transfer foil supply apparatus, a consumed transfer foil removal apparatus, and guide elements for guiding the transfer foil to and away from sheets passing through a sheet passage nip defined in part by the impression cylinder of the printing unit with which the transfer foil apparatus is integrated whereby a film image is applied on the sheets by the transfer of at least parts of an image forming layer of the transfer film onto the sheets.
2. The sheet fed offset printing machine according to claim 1 wherein the transfer foil supply apparatus comprises a foil supply roller having an associated rotary drive and the consumed foil removal apparatus comprises a foil collection roller having an associated rotary drive.
3. The sheet fed offset printing machine according to claim 2 in which a plurality of said printing units are operable for producing a colored imprint.
4. The sheet fed offset printing machine according to claim 3 in which said coating printing unit and said transfer foil apparatus comprise a coating module.
5. The sheet fed offset printing machine according to claim 4 wherein the coating module is connected downstream of the plurality of printing units so as to be able to perform a lamination on the colored imprint.
6. The sheet fed offset printing machine according to claim 4 wherein the coating module is connected upstream of the plurality of printing units.
7. The sheet fed offset printing machine according to claim 4 wherein the plurality of printing units are arranged one after the other with a turning unit being arranged between one adjacent pair of printing units for turning over printing sheets in order to print the a front side and a back side, the coating module being arranged downstream of the turning unit.
8. The sheet fed offset printing machine according to claim 4 wherein the coating module is one a plurality of coating modules arranged one after the other within the sheet-processing apparatus.
9. The sheet fed offset printing machine according to claim 8 wherein at least two adjacent coating modules are configured as an integrated operating unit.
10. The sheet fed offset printing machine according to claim 9 including a plurality of said coating modules.
11. The sheet fed offset printing machine according to claim 4 wherein the coating module is a varnishing coating module.
12. The sheet fed offset printing machine according to claim 4 wherein the coating module is configured as a printing sheet lifting apparatus.
13. The sheet fed offset printing machine according to claim 1 in which the printing unit with which said transfer foil apparatus is integrated is different from said coating printing unit.
14. The sheet fed offset printing machine according to claim 13 in which a press cylinder of said printing unit with which said transfer foil apparatus is integrated and the impression cylinder of said printing unit define the sheet passage nip within which the film image is supplied to sheets by the transfer foil.
15. The sheet fed offset printing machine according to claim 1 in which said integrated transfer foil apparatus is a part of said coating printing unit and is operable for causing the film image to be applied on sheets after the application of the image forming adhesive coating on the sheets by said coating printing unit.
16. The sheet fed offset printing machine according to claim 15 in which said transfer foil apparatus includes a press cylinder that defines a nip with the impression cylinder of the coating printing unit with which the transfer foil is integrated through which the transfer foil and sheets pass in contacting relation to each other.
17. The sheet fed offset printing machine according to claim 15 in which said coating module is a structural unit that is transportable and selectively connectable between selected printing units of the printing machine.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit for providing a clock period, the integrated circuit comprising:
a capacitor;
a switch electrically coupled with the capacitor in a parallel fashion;
a comparator including a first input node, a second input node, and a first output node, the second input node being electrically coupled with a first plate of the capacitor, the output node being electrically coupled with the switch;
a transistor, separate from the switch, electrically coupled with a second plate of the capacitor during an entire period of operation; and
a circuit electrically coupled with a gate of the transistor, the circuit being configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.
2. The integrated circuit of claim 1, wherein the circuit comprises:
a transconductance amplifier electrically coupled with the transistor and the capacitor;
an amplifier including a third input node, a fourth input node, and a second output node, wherein the third input node is electrically coupled with the transconductance amplifier;
a first resistor electrically coupled with the fourth input node; and
a second resistor electrically coupled between the fourth input node and the second output node.
3. The integrated circuit of claim 2, wherein the transconductance amplifier is configured to convert a voltage drop between a fifth input node and a sixth input node of the transconductance amplifier to the current.
4. The integrated circuit of claim 2, wherein the third input node of the amplifier is configured to receive a reference voltage (Vref), the first resistor is electrically coupled with a temperature-dependent voltage (VEB), the first resistor has a first resistance (RA), the second resistor has a second resistance (RB), and the bias voltage (Vbias) is represented by following equation:
V
bias
=
V
ref
+
(
V
ref
–
V
EB
)
\xb7
R
B
R
A
.
5. The integrated circuit of claim 4, wherein at least one of the first resistance and the second resistance is an adjustable resistance, and the bias voltage is adjustable by adjusting at least one of the first resistance and the second resistance.
6. The integrated circuit of claim 1, wherein
the circuit is configured to increase the bias voltage to increase the current flowing through the transistor and a clock period that is inversely proportional to the current is decreased, if an environmental temperature around the integrated circuit is increased, and
if the environmental temperature around the integrated circuit is decreased, the circuit is configured to increase the bias voltage to turn down the transistor such that the current is decreased and the clock period that is inversely proportional to the current is increased.
7. The integrated circuit of claim 4, wherein the reference voltage is temperature independent.
8. An integrated circuit for providing a clock period, the integrated circuit comprising:
a capacitor;
a switch coupled with the capacitor in a parallel fashion;
a comparator including a first input node, a second input node, and a first output node, the second input node being electrically coupled with the capacitor, the first output node being electrically coupled with the switch;
a first circuit electrically coupled with the first input node of the comparator, the first circuit being configured to provide a temperature-dependent reference voltage; and
a second circuit electrically coupled with the capacitor, the second circuit being configured to provide a first temperature-dependent current that is supplied to charge the capacitor, wherein the temperature-dependent reference voltage and the first temperature-dependent current are programmable, and at least one of the temperature-dependent reference voltage and the first temperature-dependent current is adjusted so as to adjust a clock period for refreshing memory cells that are electrically coupled with the integrated circuit.
9. The integrated circuit of claim 8, wherein the first circuit comprises:
a first resistor electrically coupled with the first input node of the comparator;
a first current mirror electrically coupled with the first input node of the comparator;
a second current mirror electrically coupled with the first current mirror;
a third current mirror electrically coupled with the second current mirror;
a fourth current minor electrically coupled with the second current mirror;
a second resistor electrically coupled between the fourth current mirror and a power line that is configured to provide a power voltage; and
a first amplifier including a third input node, a fourth input node, and a second output node, wherein the third input node of the first amplifier is configured to receive a first temperature-dependent voltage, the fourth input node of the first amplifier is electrically coupled with a node between the second resistor and the fourth current mirror, and the second output node of the first amplifier is electrically coupled with the fourth current mirror.
10. The integrated circuit of claim 9, wherein the first resistor has a resistance RA\u2032, the second resistor has a resistance RB\u2032, the first temperature-dependent voltage is KVEB\u2032, K is a proportional factor, VEB\u2032 is a voltage that is inversely proportional to absolute temperature, the third current mirror is configured to provide the second current mirror a first temperature-independent current, the fourth current mirror is configured to provide the second current mirror a second temperature-dependent current
(
KV
EB
\u2032
R
B
\u2032
)
,
and wherein the temperature-dependent reference voltage (Vref\u2032) is represented by following equation:
V
ref
\u2032
=
(
KV
EB
\u2032
R
B
\u2032
–
I
C
\u2062
\u2062
1
\u2032
)
\xb7
R
A
\u2032
.
11. The integrated circuit of claim 10, wherein at least one of the resistances RA\u2032 and RB\u2032 is an adjustable resistance, and the temperature-dependent reference voltage (Vref\u2032) is programmable by adjusting at least one of the resistances RA\u2032 and RB\u2032, the proportion factor K, and the first temperature-independent current (IC1\u2032).
12. The integrated circuit of claim 9, wherein the second circuit comprises:
a fifth current mirror electrically coupled with the second input node of the comparator;
a sixth current mirror electrically coupled with the fifth current mirror;
a seventh current mirror electrically coupled with the sixth current mirror;
a third resistor electrically coupled between the seventh current mirror and a power line that is configured to provide a power voltage; and
a second amplifier including a fifth input node, a sixth input node, and a third output node, wherein the fifth input node of the second amplifier is configured to receive a second temperature-dependent voltage, the sixth input node of the second amplifier is electrically coupled with a node between the third resistor and the seventh current mirror, and the second output node of the first amplifier is electrically coupled with the seventh current mirror.
13. The integrated circuit of claim 12, wherein a third resistor has a resistance RC\u2032, the second temperature-dependent voltage is VEB\u2032, the seventh current mirror is configured to provide the sixth current mirror a third temperature-dependent current
(
V
EB
\u2032
R
C
\u2032
)
,
the sixth current mirror is configured to receive a second temperature-independent current (IC2\u2032) from the first circuit, and the first temperature-dependent current (IC\u2032) is represented by following equation:
I
C
\u2032
=
(
I
C
\u2062
\u2062
2
\u2032
–
V
EB
\u2032
R
C
\u2032
)
.
14. The integrated circuit of claim 13, wherein the resistance RC\u2032 is an adjustable resistance, and the temperature-dependent current (IC\u2032) is adjustable by adjusting at least one of the resistance RC\u2032 and the third temperature-independent current (IC2\u2032).
15. The integrated circuit of claim 9, wherein
if an environmental temperature around the integrated circuit is increased, the first circuit is configured to decrease the temperature-dependent reference voltage andor the second circuit is configured to increase the first temperature-dependent current; and
if the environmental temperature around the integrated circuit is decreased, the first circuit is configured to increase the temperature-dependent reference voltage andor the second circuit is configured to decrease the first temperature-dependent current.
16. A method of operating an integrated circuit for generating a clock period for refreshing memory cells of a memory circuit, the integrated circuit including a capacitor, a switch, a comparator, and a transistor, the switch being electrically coupled with the capacitor in a parallel fashion, the comparator being electrically coupled with the switch and the capacitor, the transistor being electrically coupled with the capacitor, the method comprising:
providing a bias voltage to a gate of the transistor so as to control a current that is supplied to charge the capacitor; and
comparing a temperature-independent reference voltage received by the comparator and a voltage level on a node of the capacitor for controlling an openclose state of the switch so as to generate the clock period.
17. The method of claim 16, wherein the bias voltage is provided by a circuit including:
a transconductance amplifier electrically coupled with the transistor and the capacitor;
an amplifier electrically coupled with the transconductance amplifier;
a first resistor electrically coupled with an input node of the amplifier; and
a second resistor electrically coupled between the input node and an output node of the amplifier.
18. The method of claim 17, wherein the temperature-independent reference voltage is Vref, the first resistor is electrically coupled with a temperature-dependent voltage (VEB), the first resistor has a first resistance (RA), the second resistor has a second resistance (RB), and the bias voltage (Vbias) is represented by following equation:
V
bias
=
V
ref
+
(
V
ref
–
V
EB
)
\xb7
R
B
R
A
.
19. The method of claim 18, wherein at least one of the first resistance and the second resistance is an adjustable resistance, and the bias voltage is adjustable by adjusting at least one of the first resistance and the second resistance.
20. The method of claim 16, further comprising
the bias voltage is increased to turn up the transistor such that the current is increased and a clock period that is inversely proportional to the current is decreased, if an environmental temperature around the integrated circuit is increased; and
the bias voltage is decreased to turn down the transistor such that the current is decreased and the clock period that is inversely proportional to the current is increased, if the environmental temperature around the integrated circuit is decreased.