1. A semiconductor device comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in an upper portion of the first nitride semiconductor layer; and
an ohmic electrode formed selectively on the second nitride semiconductor layer, wherein the second nitride semiconductor layer includes a contact area having at least one inclined surface which is inclined toward an upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration and
the ohmic electrode is formed on the contact area.
2. The semiconductor device of claim 1, wherein a lowermost portion of the contact area is positioned at a distance of not less than 1 nm and not more than 1 \u03bcm from the 2-dimensional electron gas layer.
3. The semiconductor device of claim 1, wherein a bottom portion of the contact area is formed with a striped pattern which is projecting and depressed in cross section with a periodicity of not less than 1 nm and not more than 1 \u03bcm.
4. The semiconductor device of claim 1, wherein the ohmic electrode is formed to cover at least one of the inclined surface of the contact area.
5. The semiconductor device of claim 1, wherein the ohmic electrode is composed of one layer made of a metal selected from the group consisting of titanium, strontium, aluminum, niobium, vanadium, zirconium, hafnium, chromium, tungsten, molybdenum, rhodium, rhenium, cobalt, and lanthanum, of at least two layers each made of a metal selected from the group, of an alloy layer containing at least two metals selected from the group, or of a conductive compound containing at least one metal selected from the group and oxygen, nitrogen, or boron.
6. The semiconductor device of claim 1, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661), and
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio.
7. A semiconductor device comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in an upper portion of the first nitride semiconductor layer; and
an ohmic electrode formed selectively on the second nitride semiconductor layer, wherein the second nitride semiconductor layer has a contact area defining a depressed cross-sectional configuration,
the contact area has a bottom portion containing an impurity having a conductivity introduced therein and a sidewall composed of an insulating film on an inner wall surface thereof, and
the ohmic electrode is formed to cover an inner side of the contact area including the sidewall.
8. The semiconductor device of claim 7, wherein the ohmic electrode is composed of one layer made of a metal selected from the group consisting of titanium, strontium, aluminum, niobium, vanadium, zirconium, hafnium, chromium, tungsten, molybdenum, rhodium, rhenium, cobalt, and lanthanum, of at least two layers each made of a metal selected from the group, of an alloy layer containing at least two metals selected from the group, or of a conductive compound containing at least one metal selected from the group and oxygen, nitrogen, or boron.
9. The semiconductor device of claim 7, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661), and
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio.
10. A semiconductor device comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in an upper portion of the first nitride semiconductor layer;
a third nitride semiconductor layer formed on the second nitride semiconductor layer and smaller in band gap energy than the second nitride semiconductor layer; and
an ohmic electrode formed selectively on the third nitride semiconductor layer, wherein
the third nitride semiconductor layer includes a contact area having at least one inclined surface which is inclined toward an upper surface of the second nitride semiconductor layer and defining a depressed cross-sectional configuration and
the ohmic electrode is formed on the contact area.
11. The semiconductor device of claim 10, wherein the ohmic electrode is composed of one layer made of a metal selected from the group consisting of titanium, strontium, aluminum, niobium, vanadium, zirconium, hafnium, chromium, tungsten, molybdenum, rhodium, rhenium, cobalt, and lanthanum, of at least two layers each made of a metal selected from the group, of an alloy layer containing at least two metals selected from the group, or of a conductive compound containing at least one metal selected from the group and oxygen, nitrogen, or boron.
12. The semiconductor device of claim 10, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661), and
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio.
13. The semiconductor device of claim 10, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661),
a general formula of a material composing the third nitride semiconductor layer is AllInmGa1-l-mN (where l and m satisfy 0\u2266l\u22661, 0\u2266m\u22661, and 0\u2266l+m\u22661),
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio, and
a composition of the third nitride semiconductor layer and the composition of the second nitride semiconductor layer are such that 1 representing an Al ratio is smaller than u representing the Al ratio.
14. The semiconductor device of claim 1, wherein
the second nitride semiconductor layer includes two contact areas,
a gate electrode is formed on the second nitride semiconductor layer,
the gate electrode is between the one contact area and the other contact area, and
depths of the inclined surfaces of the two contact areas become shallower with approach toward the gate electrode.
15. The semiconductor device of claim 1, wherein the depressed cross-sectional configuration of the contact area is V-shaped.
16. The semiconductor device of claim 10, wherein the inclined surface of the contact area reaches into the second nitride semiconductor layer.
17. The semiconductor device of claim 16, wherein the ohmic electrode is formed to cover both the inclined surface of the third nitride semiconductor layer and the inclined surface of the second nitride semiconductor layer.
18. The semiconductor device of claim 10, wherein
the third nitride semiconductor layer includes two contact areas,
a gate electrode is formed on the third nitride semiconductor layer,
the gate electrode is between the one contact area and the other contact area, and
depths of the inclined surfaces of the two contact areas become shallower with approach toward the gate electrode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A converter, comprising:
a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output;
a switch for sinking a portion of said first signal, wherein said switch is responsive to said output; and
an integrator including a capacitor connected between said first input and a ground, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto.
2. The converter of claim 1 wherein said second signal is a reference signal.
3. The converter of claim 1 wherein said second signal is inversely proportional to the absolute temperature.
4. The converter of claim 1 wherein said switch is a transistor.
5. A converter, comprising:
a comparator having a first input operable to receive a first signal a second input operable to receive a second signal, and an output;
a switch responsive to said output for sinking a portion of said first signal, and wherein said portion of said first signal that is sunk by said switch is equal to a current that is inversely proportional to the absolute temperature; and
an integrator connected to said first input, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto.
6. A temperature measurement system, comprising:
a temperature sensor;
a converter responsive to said temperature sensor, said converter comprising:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch for sinking a portion of said first signal, wherein said switch is responsive to said output; and
an integrator including a capacitor connected between said first input and a ground, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and
a counter, responsive to said output, for producing an output signal.
7. The temperature measurement system of claim 6 wherein said second signal is a reference signal.
8. The temperature measurement system of claim 6 wherein said second signal is inversely proportional to the absolute temperature.
9. The temperature measurement system of claim 6 further comprising a plurality of temperature sensors and a multiplexer, said multiplexer operable to receive a signal from each of said plurality of temperature sensors and to conduct, to said converter, the signal from a selected one of said plurality of temperature sensors.
10. The temperature measurement system of claim 6 wherein said temperature sensor includes a vertical bipolar transistor, a lateral bipolar transistor, or a CMOS transistor.
11. The temperature measurement system of claim 6 wherein said switch is a transistor.
12. The temperature measurement system of claim 6 further comprising a controller for regulating the operation of said counter.
13. The temperature measurement system of claim 12 wherein said controller further regulates one of said converter or said temperature sensor.
14. A temperature measurement system, comprising:
a temperature sensor;
a converter responsive to said temperature sensor, said converter comprising:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch responsive to said output for sinking a portion of said first signal, and wherein said portion of said first signal that is sunk by said switch is equal to a current that is inversely proportional to the absolute temperature; and
an integrator connected to said first input, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and
a counter, responsive to said output, for producing an output signal.
15. A memory system, comprising: a memory module; a temperature measurement module; and a memory controller for communicating with said memory module and said temperature module via a system bus, wherein said temperature measurement module comprises:
at least one temperature sensor;
a converter responsive to said at least one temperature sensor, wherein said converter comprises:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch for sinking a portion of said first signal, wherein said switch is responsive to said output; and
an integrator including a capacitor connected between said first input and a ground, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and
a counter, responsive to said output, for producing an output signal.
16. The memory system of claim 15 wherein said second signal is a reference signal.
17. The memory system of claim 15 wherein said second signal is inversely proportional to the absolute temperature.
18. The memory system of claim 15 wherein said memory module is a dual-inline-memory-module having one or more synchronous dynamic random access memory devices.
19. The memory system of claim 15 wherein said temperature measurement module further comprises a plurality of temperature sensors and a multiplexer, said multiplexer operable to receive a signal from each of said plurality of temperature sensors and to conduct, to said converter, the signal from a selected one of said plurality of temperature sensors.
20. The memory system of claim 15 wherein said temperature sensor includes a vertical bipolar transistor, a lateral bipolar transistor, or a CMOS transistor.
21. The memory system of claim 15 wherein said switch is a transistor.
22. The memory system of claim 15 wherein said temperature measurement module further comprises a controller for regulating the operation of said counter.
23. The memory system of claim 22 wherein said controller further regulates one of said converter or said at least one temperature sensor.
24. A memory system, comprising: a memory module; a temperature measurement module; and a memory controller for communicating with said memory module and said temperature module via a system bus, wherein said temperature measurement module comprises:
at least one temperature sensor;
a converter responsive to said at least one temperature sensor, wherein said converter comprises:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch for responsive to said output for sinking a portion of said first signal, and wherein said portion of said first signal that is sunk by said switch is equal to a current that is inversely proportional to the absolute temperature; and
an integrator connected to said first input, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and
a counter, responsive to said output, for producing an output signal.