1. An information processing apparatus comprising:
a main body;
an optical disc drive provided in the main body, the optical disc drive configured to output an eject signal to an outside in response to an operation of an eject button; and
a drive management module provided in the main body, the drive management module configured to supply power to the optical disc drive when the eject signal is received from the optical disc drive which is in a power-off state, to determine, after supplying the power to the optical disc drive, whether the optical disc drive is in a ready state or not, and to send to a signal instructing opening of a tray of the optical disc drive when it is determined that the optical disc drive is in the ready state.
2. The information processing apparatus of claim 1, wherein the drive management module is configured to power off the optical disc drive when a non-use state of the optical disc drive has continued for a predetermined period.
3. The information processing apparatus of claim 1, wherein the drive management module is configured to power off the optical disc drive when an event of requesting power-off of the optical disc drive is occurred.
4. The information processing apparatus of claim 1, wherein the drive management module is configured to determine whether the main body is shaking or not by using an acceleration sensor in the main body when the eject signal is received from the optical disc drive which is in the power-off state, and to supply the power to the optical disc drive if the main body is not shaking.
5. An information processing apparatus comprising:
a main body;
an optical disc drive provided in the main body, the optical disc drive configured to output an eject signal to an outside, the eject signal being generated by an operation of an eject button regardless of whether the optical disc drive is in a power-on state or not; and
a drive management module provided in the main body, the drive management module configured to power off the optical disc drive, to supply power to the optical disc drive when the eject signal is received from the optical disc drive which is in a power-off state, to determine, after supplying the power to the optical disc drive, whether the optical disc drive is in a ready state or not, and to send to a signal instructing opening of a tray of the optical disc drive when it is determined that the optical disc drive is in the ready state.
6. The information processing apparatus of claim 5, wherein the drive management module is configured to determine whether the main body is shaking or not by using an acceleration sensor in the main body when the eject signal is received from the optical disc drive which is in the power-off state, and to supply the power to the optical disc drive if the main body is not shaking.
7. A drive control method of controlling an optical disc drive in an information processing apparatus, the method comprising:
powering off the optical disc drive configured to output an eject signal to an outside in response to an operation of an eject button;
supplying power to the optical disc drive when the eject signal is received from the optical disc drive which is in a power-off state;
determining, after supplying the power to the optical disc drive, whether the optical disc drive is in a ready state or not, and
sending to a signal instructing opening of a tray of the optical disc drive when it is determined that the optical disc drive is in the ready state.
8. The drive control method of claim 7, further comprising determining whether the information processing apparatus is shaking or not by using an acceleration sensor in the information processing apparatus when the eject signal is received from the optical disc drive which is in the power-off state, wherein the supplying the power to the optical disc drive is performed if the information processing apparatus is not shaking.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus for extracting data from virtually concatenated (VCAT) plesiochronous digital hierarchy (PDH) streams carried in a synchronous digital hierarchy (SDH) signal, comprising:
an SDH overhead and pointer processor coupled to a SONET network;
a first telecom bus coupled to said SDH overhead and pointer processor;
a second telecom bus coupled to an SDH VCAT demapper;
a plurality of PDH units coupled between said first telecom bus and said second telecom bus, said plurality of PDH units providing PDH demapping and PDH frame synchronization according to a gapped clock produced by said PDH demapping to generate at least one serialized bit stream as well as providing serial to parallel conversion of said at least one serialized bit stream into bytes for supply to said second telecom bus;
a signal path connecting said first telecom bus and said second telecom bus, said signal path distinct from said plurality of PDH units; and
a configuration block for selectively controlling operation of said SDH VCAT demapper in one of a first mode and second mode, wherein
in said first mode, bytes produced by said SDH overhead and pointer processor are supplied to said SDH VCAT demapper over said first telecom bus, said signal path and said second telecom bus, and
in said second mode, bytes produced by said SDH overhead and pointer processor are supplied to said plurality of PDH units over said first telecom bus for processing and output to said SDH VCAT demapper over said second telecom bus;
wherein said SDH VCAT demapper deskews members of a virtual concatenated group (VCG) associated with frames containing virtual concatenation link capacity adjustment scheme information (VLI) by
selecting an acceptable delay which is less than the maximum compensable delay between members,
dividing each VLI frame into chunks,
assigning each chunk a number based on the multi-frame indicator (MFI) range and the number of chunks per VLI frame, and
temporarily storing chunks in a memory at an address dictated by a remainder function, the remainder function operating on the acceptable delay and a respective chunk number.
2. An apparatus according to claim 1, further comprising:
a GFP demapper coupled to said SDH VCAT demapper.
3. An apparatus according to claim 2, further comprising:
an Ethernet MAC coupled to said GFP demapper.
4. An apparatus according to claim 1, wherein:
said PDH units include PDH demappers and PDH frame synchronizers.
5. An apparatus according to claim 4, further comprising:
a control decoder coupled to said first telecom bus, to said SDH VCAT demapper, and to said PDH demappers.
6. An apparatus according to claim 5, further comprising:
a low order pointer processor coupled to said first telecom bus, to said control decoder, and to said SDH VCAT demapper.
7. A method according to claim 1, wherein:
the remainder function includes long division.
8. A method according to claim 7, wherein:
the long division is performed iteratively before a remainder is determined and the remainder is used to address the memory.
9. A method according to claim 7, wherein:
the divisor of the long division is configurable.
10. A method according to claim 1, wherein:
the memory address for temporary storage of chunks is calculated according to the equation
Address(i)=(Chunk_Value%Address_Range_for_VCG)+i*Address_Range_for_VCG
where \u201ci\u201d is the member number, \u201c%\u201d is a remainder function and Address_Range_for_VCG is the maximum delay to be compensated.
11. A method for extracting data from virtually concatenated (VCAT) plesiochronous digital hierarchy (PDH) streams carried in a synchronous digital hierarchy (SDH) signal, comprising:
processing the SDH signal with an SDH overhead and pointer processor to generate bytes corresponding thereto;
in a first mode, transferring bytes generated by the SDH overhead and pointer processor to a first telecom bus and then to a second telecom bus over a signal path connecting said first telecom bus to said second telecom bus for output to an SDH VCAT demapper coupled to said second telecom bus; and
in a second mode, transferring bytes generated by the SDH overhead and pointer processor to a first telecom bus and then to a plurality of PDH units coupled to the first telecom bus, said plurality of PDH units providing PDH demapping and PDH frame synchronization according to a gapped clock produced by said PDH demapping to generate at least one serialized bit stream as well as providing serial to parallel conversion of said at least one serialized bit stream into bytes for supply to said second telecom bus and output to said SDH VCAT demapper coupled to said second telecom bus;
wherein said SDH VCAT demapper deskews members of a virtual concatenated group (VCG) associated with frames containing virtual concatenation link capacity adjustment scheme information (VLI) by
selecting an acceptable delay which is less than the maximum compensable delay between members,
dividing each VLI frame into chunks,
assigning each chunk a number based on the multi-frame indicator (MFI) range and the number of chunks per VLI frame, and
temporarily storing chunks in a memory at an address dictated by a remainder function, the remainder function operating on the acceptable delay and a respective chunk number.
12. A method according to claim 11, further comprising:
demapping GFP frames output from said SDH VCAT demapper.
13. The method according to claim 12, further comprising:
extracting Ethernet frames from the GFP frames.
14. A method according to claim 11, wherein:
the remainder function includes long division.
15. A method according to claim 14, wherein:
the long division is performed iteratively before a remainder is determined and the remainder is used to address the memory.
16. A method according to claim 14, wherein:
the divisor of the long division is configurable.
17. A method according to claim 11, wherein:
the memory address for temporary storage of chunks is calculated according to the equation
Address(i)=(Chunk_Value%Address_Range_for_VCG)+i*Address_Range_for_VCG
where \u201ci\u201d is the member number, \u201c%\u201d is a remainder function and Address_Range_for_VCG is the maximum delay to be compensated.
18. A method for processing a synchronous digital hierarchy (SDH) signal carrying a virtual concatenated group (VCG), the VCG associated with frames containing virtual concatenation link capacity adjustment scheme information (VLI), the method comprising:
a) providing a demapper that processes members of the VCG; and
b) operating the demapper to deskew members of the VCG by
i) selecting an acceptable delay which is less than the maximum compensable delay between members;
ii) dividing each VLI frame into chunks;
iii) assigning each chunk a number based on the multi-frame indicator (MFI) range and the number of chunks per VLI frame; and
iv) temporarily storing chunks in a memory at an address dictated by a remainder function, the remainder function operating on the acceptable delay and a respective chunk number.
19. A method according to claim 18, wherein:
the remainder function includes long division.
20. A method according to claim 19, wherein:
the long division is performed iteratively before a remainder is determined and the remainder is used to address the memory.
21. A method according to claim 19, wherein:
the divisor of the long division is configurable.
22. A method according to claim 18, wherein
the memory address for temporary storage of chunks is calculated according to the equation
Address(i)=(Chunk_Value%Address_Range_for_VCG)+i*Address_Range_for_VCG
where \u201ci\u201d is the member number, \u201c%\u201d is a remainder function and Address_Range_for_VCG is the maximum delay to be compensated.