1. A diode pumped solid state laser system, comprising:
two or more diode pumped solid state laser cavities able to produce beams of two or more respective wavelengths travelling in associated paths;
a controller to selectively control activation of at least one of the two or more diode pumped solid state laser cavities and to selectively control associated power levels of the produced beams of the at least one of the two or more diode pumped solid state laser cavities; and
an optical configuration to align the associated paths of said beams along a common optical axis.
2. (canceled)
3. The system of claim 1, wherein at least one said laser cavities comprises a primary laser section and a frequency doubling section.
4. The system of claim 1, wherein said primary laser section comprises a pump diode laser source.
5. The system of claim 1, wherein said optical configuration comprises at least one fold mirror.
6. The system of claim 1, wherein said optical configuration comprises one or more combiner mirrors to combine the paths of at least two laser beams.
7. The system of claim 1, comprising a plurality of optical ports associated with an output of said optical configuration.
8. The system of claim 1, comprising at least one delivery system to deliver at least one of said laser beams to a target area.
9. The system of claim 1, wherein said two or more diode pumped solid state laser cavities are three diode pumped solid state laser cavities, able to produce beams of three respective wavelengths.
10. An illumination method, comprising:
controlling activation of at least one of two or more diode pumped solid state laser cavities and power levels of beams produced by the at least one of the two or more diode pumped solid state laser cavities, the beams traveling in associated paths;
aligning the paths of two or more diode pumped solid state generated laser beams having two or more respective wavelengths on a common optical path; and
delivering at least one of said laser beams to a target area.
11. The method of claim 10, comprising:
passing said two or more laser beams through two or more respective fold mirrors; and
combining the paths of at least two said respective laser beams using one or more combiner mirrors.
12. The method of claim 10, further comprising delivering an aiming beam substantially along said optical path.
13. The method of claim 10, comprising channeling said two or more respective laser beams via one or more optical ports.
14. The method of claim 10, comprising delivering said respective laser beams using one or more delivery systems.
15. An apparatus to combine the paths of respective laser beams of two or more wavelengths, comprising:
a collimation lens to collimate at least two diode pumped solid state laser generated beams of different wavelengths; and
an optical configuration to align the paths of the collimated beams along a common optical axis.
16. The apparatus of claim 15, wherein said optical configuration includes at least one combiner mirror.
17. The apparatus of claim 15, comprising a moving attenuator to attenuate at least one of said beams.
18. The apparatus of claim 15, comprising at least one power-monitoring detector to detect the power of at least one of said beams on said common optical axis.
19. The apparatus of claim 15, comprising at least one pickoff mirror to reflect at least one or said beams to a diffuser.
20. The apparatus of claim 15, comprising a safety shutter to limit the exposure of said target to said beams.
21. The apparatus of claim 15, comprising an aiming beam to enable aiming of said beam towards a target.
22. The apparatus of claim 15, comprising at least one optical port associated with said common optical axis.
23. The apparatus of claim 15, comprising at least one optical socket.
24. The apparatus of claim 15, comprising one or more laser delivery systems to deliver at least one of said beams to a target.
25. A method to operate a laser illumination system at one or more selected wavelengths, comprising:
selecting a desired wavelength to be delivered;
selecting a diode pump laser source to activate;
selecting laser exposure settings for the selected wavelength; and
activating said selected laser source to generate a beam with a desired wavelength.
26. The method of claim 25, further comprising:
processing feedback from a detector, for said generated beam; and
validating accuracy of the actual power output of said generated beam.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory, comprising:
a plurality of memory cells, each of the memory cells including a memory element with first and second terminals, and first and second diodes as program selectors, each of the first and second diodes having a first terminal associated with a first active region with a first type of dopant and a second terminal associated with a second active region with a second type of dopant, both the first and second active regions being fabricated from sources or drains of CMOS devices and residing in a common well, the first diode having the first terminal coupled to the second terminal of the memory element, and the second diode having the second terminal coupled to the second terminal of the memory element;
a plurality of local wordlines, each coupled to a plurality of the memory cells via the second terminal of the first diodes or to the first terminal of the second diodes and having a first resistivity;
a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity; and
a plurality of bitlines, each coupled to a plurality of the memory cells via the first terminal of memory element;
wherein, for each of the memory cells, the memory element is configured to be programmable by turning on the first diode while cutting off the second diode for one state and by turning on the second diode while cutting off the first diode for another state.
2. A memory as recited in claim 1, wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagentic as a fixed layer stack, another multi-layer of ferromagnetic or anti-ferromagentic stack as a free layer stack, and a dielectric layer in between the stacks.
3. A memory as recited in claim 1, wherein the memory element comprises a metal-oxide film between metal or metal alloy electrodes.
4. A memory as recited in claim 1, wherein the memory element comprises a solid-state electrolyte film between metal or metal alloy electrodes.
5. A memory as recited in claim 1, wherein the well is shallower than the Shallow Trench Isolation (STI) for isolating CMOS devices.
6. A memory as recited in claim 1, wherein the well is fabricated for CMOS devices.
7. A memory as recited in claim 1, wherein the local wordline is at least in part constructed from a well.
8. A memory as recited in claim 1, wherein the global wordline is constructed of metal.
9. A memory as recited in claim 1, wherein the global wordline is coupled to the local wordline through at least one of conductive via or contact.
10. A memory as recited in claim 1, wherein the bitline is coupled to a first supply voltage and the global wordline is coupled to a second supply voltage during program or read, and wherein the voltage between the first and second supply voltages has a larger magnitude or longer duration for program than read.
11. A memory as recited in claim 1, wherein the bitline is coupled to a first supply voltage line and the global wordline is coupled to a second supply voltage line during program, and wherein the voltage between the first and second supply voltages lines has one polarity for one state and another polarity for another state.
12. A memory as recited in claim 1, wherein the memory further comprising a plurality of write bitline selectors to select a bitline coupled to a first supply voltage and a plurality of wordline drivers to select a local wordline coupled to a second supply voltage to conduct a current during program.
13. A memory as recited in claim 1, wherein the memory further comprising a plurality of read bitline selectors to select a bitline coupled to a sense amplifier and a plurality of wordline drivers to select a local wordline coupled to a supply voltage to conduct a current through the sense amplifier during read.
14. An electronics system, comprising:
a processor;
a memory operatively connected to the processor, the memory including at least:
a plurality of memory cells, each of the memory cells including a memory element with first and second terminal, and first and second diodes as program selectors, each of the first and second diodes having a first terminal associated with a first active region with a first type of dopant and a second terminal associated with a second active region with a second type of dopant, both of the first and second active regions being fabricated from sources or drains of CMOS devices and residing in a common well, the first diode having the first terminal coupled to the second terminal of the memory element, and the second diode having the second terminal coupled to the second terminal of the memory element;
a plurality of local wordlines, each coupled to a plurality of the memory cells via the second terminal of the first diodes or to the first terminal of the second diodes and having a first resistivity;
a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity; and
a plurality of bitlines, each coupled to a plurality of the memory cells via the first terminal of memory element,
wherein for each of the memory cells, the memory element is configured to be programmable by turning on the first diode while cutting off the second diode for one state and by turning on the second diode while cutting off the first diode for another state.
15. An electronics system as recited in claim 14, wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagentic as a fixed layer stack, another multi-layer of ferromagnetic or anti-ferromagentic stack as a free layer stack, and a dielectric layer in between the stacks.
16. An electronic system as recited in claim 14, wherein, in each of the memory cells, the second terminal of the first diode is coupled to the first terminal of the second diode.
17. An electronics system as recited in claim 14, wherein the electronics system is configured to periodically read content of each of the memory cells and writes the content back.
18. A method for programming a memory, comprising:
providing a plurality of memory cells, each memory cell including a memory element with first and second terminals, and first and second diodes as program selectors, each of the first and second diodes having a first terminal associated with a first active region with a first type of dopant and a second terminal associated with a second active region with a second type of dopant, both of the first and second active regions being fabricated from sources or drains of CMOS devices and residing in a common well, wherein the first diode having a first terminal coupled to the second terminal of the memory element, and the second diode having the second terminal coupled to the second terminal of the memory element;
providing a plurality of local wordlines, each coupled to a plurality of the memory cells in the second terminal of the first diode or the first terminal of the second diode and having a first resistivity;
providing a plurality of global wordlines, each coupled to at least one of the local wordlines and having a second resistivity;
providing a plurality of bitlines, each coupled to a plurality of the memory cells via the first terminal of memory element; and
programming at least one selected memory cell selected from the plurality of memory cells by applying a first supply voltage to at least one selected bitline and applying a second supply voltage to at least one select global wordline.
19. A method as recited in claim 18, wherein the memory element is a Magnetic Tunnel Junction (MTJ) that has a multi-layer of ferromagnetic or anti-ferromagentic as a fixed-layer stack, another multi-layer of ferromagnetic or anti-ferromagentic stack as a free-layer stack, and a dielectric layer in between the stacks.
20. A method as recited in claim 18, wherein the at least one selected memory cell is programmed to one state by conducting the first diode in one current direction, and the at least one selected memory cell is programmed to another state by conducting the second diode in another current direction.