1. A wafer box conveyer comprising:
a chassis comprising a frame and a plurality of wheels mounted under the frame;
a transverse moving mechanism, movably connected to the frame;
a longitudinal moving mechanism, movably connected to the transverse moving mechanism, wherein a moving direction of the longitudinal moving mechanism is perpendicular to that of the transverse moving mechanism;
a loading mechanism comprising at least one tray for a wafer box; and
a shock reduction mechanism disposed between the at least one tray and the frame for absorbing a load of the tray.
2. The wafer box conveyer of claim 1, further comprising a positioning mechanism wherein the positioning mechanism comprises a base, a pedal operator, a clipping block and a link, the base is fixed to a front side of the frame, and the clipping block is in the internal part of base and connects the pedal operator through the link.
3. The wafer box conveyer of claim 1, wherein the frame comprises at least one post, at least one horizontal rod and at least one crossed rod, each of the horizontal rods is connected between every two adjacent posts, and the crossed rods are crosswise located between two opposite rods.
4. The wafer box conveyer of claim 3, wherein the wheels are separately mounted on ends of the posts.
5. The wafer box conveyer of claim 4, wherein each the post is provided with at least one set of grips, each set of grips 13 is on the different side of the frame.
6. The wafer box conveyer of claim 1, wherein the transverse moving mechanism comprises at least one pair of first rails and at least one pair of first guiding seats slidably connected to the at least one pair of first rails.
7. The wafer box conveyer of claim 6, wherein the transverse moving mechanism comprises a pair of vertical plates and a moving seat, the vertical plates are fixed to the frame for being mounted by the at least one pair of first rails, the moving seat connects the at least one pair of first guiding seat to allow the moving seat to horizontally move on the frame.
8. The wafer box conveyer of claim 7, wherein the longitudinal moving mechanism comprises a pair of second rails fixed on the moving seat and a second guiding seat slidably connected to the second rails.
9. The wafer box conveyer of claim 8, wherein the longitudinal moving mechanism comprises an arm assembly and the arm assembly is fixed on the second guiding seat to move vertically.
10. The wafer box conveyer of claim 9, wherein the arm assembly comprises a connecting rod and a pair of arms separately mounted at two ends of the connecting rod, and the connecting rod is fixed at the second guiding seat.
11. The wafer box conveyer of claim 8, further comprising an elevator, wherein the elevator comprises a rotating rod, a cam, and a passive element, the rotating rod is pivotally connected on the transverse moving mechanism, the cam is connected to the rotating rod, the cam is formed with an arcked trough, two ends of the passive element are fixed to the second guiding seat and a protrusion respectively, and the protrusion is inserted in and confined to the arcked trough.
12. The wafer box conveyer of claim 11, wherein the elevator further comprises a pneumatic cylinder and a controller, one end of the pneumatic cylinder is fixed to the moving seat 24 and the other end is connected to the second guiding seat, and the controller is mounted on the rotating rod for controlling the pneumatic cylinder.
13. The wafer box conveyer of claim 11, further comprising a locking mechanism, wherein the locking mechanism comprises a stem, a cord and a stopper, the stem is fixed to the rotating rod, the cord connects the stem and stopper, and the stopper is equipped corresponding to the at least one pair of the first rails for limiting the moving seat.
14. The wafer box conveyer of claim 1, wherein the shock reduction mechanism comprises at least one supporting plate and shock absorbers, the at least one supporting plate is disposed between the horizontal rods and vertical plates, and the shock absorbers are fixed on the at least one supporting plates and correspond to the at least one tray.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a substrate;
a semiconductor multi-layered structure formed on the substrate, the multi-layered structure comprising an emitter layer, a base layer and a collector layer composed of a group III-V n-type compound semiconductor, the base layer lying between the emitter layer and the collector layer;
a quantum dot barrier layer lying between the emitter layer and the base layer;
a collector electrode, a base electrode and an emitter electrode respectively connected to the collector layer, base layer and emitter layer;
wherein the quantum dot barrier layer comprising a plurality of quantum dots and first and second barrier layers sandwiching the quantum dots from the emitter layer side and the base layer side, respectively, and the first and second barrier layers being composed of a semiconductor having a band gap greater than that of the semiconductor composing the quantum dots;
each of the quantum dots having a convex portion that is convex to the base layer; and
a base layer side interface in the second barrier layer, a collector layer side interface in the base layer, and an emitter layer side interface in the base layer each having curvatures that are convex to the collector layer so as to correspond to the convex portions of the quantum dots.
2. A semiconductor device according to claim 1, wherein the quantum dot is formed in a cone-like shape that is convex to the base layer.
3. A semiconductor device according to claim 2, wherein the outer diameter of the bottom surface of each quantum dot is not less than 2 nm and not more than 30 nm, and the height of the quantum dot is not less than 2 nm and not more than 10 nm.
4. A semiconductor device according to claim 1, wherein the thickness of the quantum dot barrier layer is not less than 1.5 nm and not more than 10 nm.
5. A semiconductor device according to claim 1, wherein the emitter layer, base layer and collector layer are layered in this order on the substrate.
6. A semiconductor device according to claim 1, wherein the distance h1 from a flat portion of the base layer side interface to the top of the curvatures in the second barrier layer, and the distance h2 from a flat portion of the collector layer side interface to the top of the curvature in the base layer satisfy the formula {fraction (15)}\u2266h2h1\u22661.
7. A semiconductor device according to claim 1, wherein the in-plane density of quantum dots is not less than 1010cm2 and not more than 1012cm2.
8. A semiconductor device according to claim 1, wherein the base electrode is formed on the base layer, which is exposed by removing a portion of the collector layer, and
a high-resistance region is formed between the base layer and the emitter layer at the portion corresponding to the base electrode.
9. A method for fabricating a semiconductor device comprising the steps of:
an emitter layer formation step for forming an emitter layer composed of a group III-V n-type compound semiconductor on a substrate;
a step for forming a first barrier layer on the emitter layer;
a quantum dot formation step for forming a plurality of quantum dots on the first barrier layer, each quantum dot having a convex portion with an upward convex orientation on the upper surface of the quantum dot;
a barrier layer formation step for forming a second barrier layer over the quantum dots, the second barrier layer covering the quantum dots and having curvatures with an upward convex orientation on the upper surface of the second barrier layer so as to correspond to the shape of the convex portions of the quantum dots;
a base layer formation step for forming a base layer composed of a group III-V n-type compound semiconductor on the second barrier layer, the base layer having curvatures with an upward convex orientation on upper surface of the base layer so as to correspond to the shape of the convex portions of the quantum dots;
a collector layer formation step for forming a collector layer composed of a group III-V n-type compound semiconductor on the base layer; and
an electrode formation step for forming an emitter electrode, a base electrode and a collector electrode connected to the emitter layer, the base layer and the collector layer, respectively.
10. A method for fabricating a semiconductor device according to claim 9, wherein the quantum dots are formed in an S-K mode.
11. A method for fabricating a semiconductor device according to claim 10, wherein the quantum dots are formed by irradiation with a molecular beam.
12. A method for fabricating a semiconductor device according to claim 9, which further comprises, prior to the electrode formation step:
a step for exposing a portion of the base layer by removing the collector layer above the base layer; and
a step for forming a high-resistance region between the exposed portion of the base layer and the emitter layer by implanting ions into the exposed base layer.
13. A method for fabricating a semiconductor device according to claim 9, which further comprises, prior to the electrode formation step:
a step for forming a stepped shape between the emitter layer and the base layer, by removing the base layer and the collector layer above the emitter layer to expose a portion of the emitter layer and removing the collector layer above the base layer in the portion adjacent to the exposed portion of the emitter layer to expose a portion of the base layer; and
a step for oxidizing a portion of the exposed semiconductor layers in the stepped shape section by supplying water vapor.
14. A method for fabricating a semiconductor device according to claim 13, wherein the first and the second barrier layers contain Al, and these barrier layers are oxidized by the water vapor.
15. A method for fabricating a semiconductor device according to claim 9, wherein the quantum dots are formed into a cone-like shape with their tips convex to the base layer.
16. A method for fabricating a semiconductor device according to claim 15, wherein the outer diameter of the bottom surface of each quantum dot is not less than 2 nm and not more than 30 nm, and the height of each quantum dot is not less than 2 nm and not more than 10 nm.
17. A method for fabricating a semiconductor device according to claim 9, wherein the distance h1 from a flat portion of the base layer side interface to the top of the curvatures in the second barrier layer, and the distance h2 from a flat portion of the collector layer side interface to the top of the curvatures in the base layer satisfy the formula {fraction (15)}\u2266h2h1\u22661.
18. A method for fabricating a semiconductor device according to claim 9, wherein the in-plane density of the quantum dots is not less than 1010cm2 and not more than 1012cm2.