1. An apparatus comprising:
a driver to generate an output voltage signal at an output node;
an error sensor to sense error in the output voltage signal based on a reference voltage signal and to control the driver based on the sensed error; and
a variable reference signal generator to generate the reference voltage signal and to vary the reference voltage signal as the error sensor controls the driver.
2. The apparatus of claim 1, wherein the variable reference signal generator is to generate the reference voltage signal at a first voltage level and then at a second voltage level lower than the first voltage level.
3. The apparatus of claim 1, wherein the variable reference signal generator is to generate a step voltage signal.
4. The apparatus of claim 1, wherein the variable reference signal generator is to generate a pulse voltage signal.
5. The apparatus of claim 1, comprising:
a voltage generator to generate another output voltage signal at the output node; and
a controller to control transitions between output voltage signals at the output node.
6. The apparatus of claim 5, wherein the variable reference signal generator is to vary the reference voltage signal to help prevent or reduce voltage droop at the output node in transitioning between output voltage signals.
7. An apparatus comprising:
a driver to generate an output voltage signal at an output node;
an error amplifier to control the driver based on the output voltage signal and a reference voltage signal;
a reference signal generator to output a selected one of a plurality of voltage signals as the reference voltage signal; and
a reference signal controller to control the reference signal generator as the error amplifier controls the driver to select a first one of the plurality of voltage signals as the reference voltage signal and to subsequently select a second one of the plurality of voltage signals as the reference voltage signal.
8. The apparatus of claim 7, wherein the reference signal generator comprises a multiplexer to output a selected one of a plurality of voltage signals as the reference voltage signal.
9. The apparatus of claim 7, wherein the reference signal generator comprises a resistive network to generate a plurality of voltage signals.
10. The apparatus of claim 7, wherein the reference signal controller comprises a pulse generator to output a pulsed reference select signal to the reference signal generator.
11. The apparatus of claim 7, wherein the error amplifier is to generate a control signal based on the output voltage signal and the reference voltage signal, and
wherein the driver comprises a transistor to couple a supply voltage node to the output node in response to the control signal.
12. The apparatus of claim 7, comprising:
a voltage generator to generate another output voltage signal at the output node; and
a controller to control transitions between output voltage signals at the output node.
13. The apparatus of claim 12, wherein the reference signal controller is to select a first one of the plurality of voltage signals having a higher voltage level than the second one of the plurality of voltage signals to help maintain a voltage level at the output node above a reset level in transitioning between output voltage signals.
14. The apparatus of claim 12, wherein the controller is to generate a control signal to activate the voltage generator, and
wherein the voltage generator comprises a transistor to couple a supply voltage node to the output node in response to the control signal.
15. A method comprising:
generating a reference voltage signal;
sensing error in an output voltage signal at an output node based on the reference voltage signal;
controlling the output voltage signal based on the sensed error; and
varying the reference voltage signal as the output voltage signal is controlled.
16. The method of claim 15, wherein the generating comprises generating a reference voltage signal at a first voltage level, and
wherein the varying comprises varying the reference voltage signal to a second voltage level lower than the first voltage level.
17. The method of claim 15, wherein the generating comprises selecting a first one of a plurality of voltage signals as the reference voltage signal, and
wherein the varying comprises selecting a second one of the plurality of voltage signals as the reference voltage signal.
18. The method of claim 15, comprising:
activating a voltage generator to perform the generating, sensing, controlling, and varying; and
deactivating another voltage generator from generating another output voltage signal at the output node.
19. A system comprising:
a battery; and
an integrated circuit having a voltage regulator coupled to receive an input supply voltage signal from the battery to generate a regulated output supply voltage signal at an output node, the voltage regulator including a driver to generate the output supply voltage signal, an error sensor to sense error in the output supply voltage signal based on a reference voltage signal and to control the driver based on the sensed error, and a variable reference signal generator to generate the reference voltage signal and to vary the reference voltage signal as the error sensor controls the driver.
20. The system of claim 19, wherein the voltage regulator includes a voltage generator to generate another output voltage signal at the output node and a controller to control transitions between output voltage signals at the output node.
21. The system of claim 20, wherein the variable reference signal generator is to vary the reference voltage signal to help prevent or reduce voltage droop at the output node in transitioning between output voltage signals.
22. The system of claim 20, wherein the integrated circuit forms at least a portion of a chipset.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A gate stack structure for use in a nonvolatile memory device, comprising:
a semiconductor substrate;
a gate stack formed on the semiconductor substrate, the gate stack having a sidewall and a top surface; and
a multi-layer sidewall spacer structure formed on the sidewall of the gate stack;
wherein the multi-layer sidewall spacer structure including a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer which are sequentially stacked.
2. The gate stack structure of claim 1, wherein the second oxide layer comprises an etched-back sidewall spacer.
3. The gate structure of claim 1, wherein the second oxide layer comprises a conformal sidewall spacer that overlies the top surface of the gate stack.
4. The gate structure of claim 1, wherein the gate stack comprises:
a first insulating layer, a floating gate, a second insulating layer and a control gate to form a nonvolatile memory cell.
5. The gate structure of claim 1, wherein the gate stack comprises a silicon-oxidenitride-oxide-semiconductor (SONOS) structure.
6. A nonvolatile memory cell, comprising:
a semiconductor substrate having a field region and an active region;
a gate stack formed on the active region, the gate stack having a sidewall and a top surface, the gate stack comprising a first insulating layer, a floating gate, a second insulating layer and a control gate;
a pair of source and drain regions formed on opposite sides of the gate stack within the active region;
a first oxide layer formed on the gate stack, the first oxide layer covering the sidewall of the gate stack;
a first nitride layer formed on the first oxide layer, the first nitride layer covering the sidewall of the gate stack;
a second oxide layer formed on the first nitride layer, the second oxide layer covering the sidewall of the gate stack; and
a second nitride layer formed on the second oxide layer, the second nitride layer covering the sidewall of the gate stack.
7. The nonvolatile memory cell of claim 6, wherein said first oxide layer has a thickness of approximately 5-30 nm.
8. The nonvolatile memory cell of claim 6, wherein said first nitride layer has a thickness of approximately 5-30 nm.
9. The nonvolatile memory cell of claim 6, wherein said second oxide layer has a thickness of greater than approximately 30 nm.
10. The nonvolatile memory cell of claim 6, wherein said second nitride layer has a thickness of greater than approximately 10 nm.
11. The nonvolatile memory cell of claim 6, wherein said second oxide layer comprises an etched-back sidewall spacer.
12. The nonvolatile memory cell of claim 6, wherein the first oxide layer is formed on a portion of the source and drain regions, and wherein the first and second nitride layers are formed sequentially on the first oxide layer on the source and drain regions.
13. The nonvolatile memory cell of claim 12, further comprising an interlevel dielectric layer overlying the gate stack, the interlevel dielectric layer having a borderless contact therein electrically connected to the drain region, wherein the first and second nitride layers are formed sequentially overlying a portion of the field region.
14. The nonvolatile memory cell of claim 6, wherein said second oxide layer conformally covers the top surface of the gate stack.
15. The nonvolatile memory cell of claim 6, wherein the first oxide layer is formed on the source and drain regions, and wherein the first nitride layer, the second oxide layer and the second nitride layer are sequentially formed on the first oxide layer on the source and drain regions.
16. The nonvolatile memory cell of claim 15, further comprising an interlevel dielectric layer formed over the gate stack, and a conductive layer formed in the interlevel dielectric layer electrically connected to the drain region.
17. The nonvolatile memory cell of claim 15, further comprising an interlevel dielectric layer overlying the gate stack, the interlevel dielectric layer having a borderless contact therein electrically connected to the drain region, wherein the first oxide layer, the first nitride layer, the second oxide layer, and second nitride layers are sequentially formed on a region of the field region.
18. A nonvolatile memory device including a cell transistor and a peripheral circuit transistor on a semiconductor substrate, the cell transistor including a first gate stack and the peripheral circuit transistor including a second gate stack, the first and second gate stacks each having a sidewall and a top surface,
the first gate stack further comprising:
a first oxide layer formed on the first gate stack, the first oxide layer covering the sidewall of the first gate stack;
a first nitride layer formed on the first oxide layer, the first nitride layer covering the sidewall of the first gate stack;
a second oxide layer formed on the first nitride layer, the second oxide layer conformally overlying the top surface of the first gate stack and covering the sidewall of the first gate stack; and
a second nitride layer formed on the second oxide layer, the second nitride layer covering the sidewall of the first gate stack,
the second gate stack further comprising:
a first oxide layer formed on the second gate stack;
a first nitride layer formed on the first oxide layer, the first nitride layer covering the sidewall of the second gate stack;
an etched-back oxide sidewall spacer formed on the first nitride layer, the etch-back oxide sidewall spacer covering the sidewall of the second gate stack; and
a second nitride layer formed on the resulting structure including the etched-back oxide spacer, the second nitride layer covering the sidewall of the second gate stack.
19. The nonvolatile memory device of claim 18,
wherein the first gate stack comprises:
a gate dielectric lay layer, a floating gate on the gate dielectric layer, an intergate dielectric layer on the floating gate, and a control gate on the intergate dielectric layer to form a nonvolatile memory cell, and
wherein the second gate stack comprises:
a gate dielectric layer, a gate electrode on the gate dielectric layer to form a peripheral circuit transistor.
20. A NOR-type nonvolatile memory cell, comprising:
a semiconductor substrate;
a gate stack formed on the semiconductor substrate, the gate stack having a sidewall and a top surface;
a pair of source and drain regions on opposite sides of the gate stack, the drain region having an abrupt junction within the semiconductor substrate;
a first oxide layer formed on the gate stack, the first oxide layer covering the sidewall of the gate stack;
a first nitride layer formed on the first oxide layer, the first nitride layer covering the sidewall of the gate stack;
a second oxide layer formed on the first nitride layer, the second oxide layer covering the sidewall of the gate stack; and
a second nitride layer formed on the second oxide layer, the second nitride layer covering the sidewall of the gate stack.
21. A nonvolatile memory device including a cell transistor and a peripheral circuit transistor formed on a semiconductor substrate, the cell transistor including a first gate stack and the peripheral circuit transistor including a second gate stack, the first and second gate stacks each having a sidewall and a top surface, first sourcedrain regions formed adjacent the first gate stack and second sourcedrain regions formed adjacent the second gate stack, the nonvolatile memory device, comprising:
a first oxide layer formed on the first and second gate stacks, the first oxide layer covering the sidewall of the first and second gate stacks;
a first nitride layer formed on the first oxide layer, the first nitride layer covering the sidewall of the first and second gate stacks,
a conformal oxide spacer layer covering the sidewall and the top surface of the first gate stack;
an etched-back oxide sidewall spacer formed on the first nitride layer, the etched-back oxide sidewall spacer covering the sidewall of the second gate stack; and
a second nitride layer formed on the conformal oxide spacer layer and the etched-back oxide sidewall spacer, the second nitride layer covering the sidewall of the first and second gate stacks,
wherein each of the first sourcedrain regions has a single highly-doped impurity region and each of the second sourcedrain regions has a LDD structure.
22. The nonvolatile memory device of claim 21, wherein the first sourcedrain regions includes a lightly-doped impurity region, shielding the single highly-doped impurity region.